Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751039AbdGGLRA (ORCPT ); Fri, 7 Jul 2017 07:17:00 -0400 Received: from mail2.skidata.com ([91.230.2.91]:22730 "EHLO mail2.skidata.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752019AbdGGLQ5 (ORCPT ); Fri, 7 Jul 2017 07:16:57 -0400 X-IronPort-AV: E=Sophos;i="5.40,322,1496095200"; d="scan'208";a="761931" Subject: Re: [PATCH 2/2] net: ethernet: fsl: add phy reset after clk enable option To: Andy Duan , "robh+dt@kernel.org" , "mark.rutland@arm.com" References: <1499346330-12166-1-git-send-email-richard.leitner@skidata.com> <1499346330-12166-2-git-send-email-richard.leitner@skidata.com> <81105c77-d48f-271b-2de1-c877b9413184@skidata.com> <6de114cb-4521-4bb2-d0a3-4aea32936bd3@skidata.com> CC: "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dev@g0hl1n.net" , Andrew Lunn From: Richard Leitner Message-ID: Date: Fri, 7 Jul 2017 13:16:54 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.24.42] X-ClientProxiedBy: sdex1srv.skidata.net (172.16.10.92) To sdex1srv.skidata.net (172.16.10.92) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1061 Lines: 23 Hi Andy, thanks for the clarifications! On 07/07/2017 01:08 PM, Andy Duan wrote: >> 3. Who should then trigger the "hard reset" of the PHY? phy_init_hw? The FEC? >> >> The point is that the LAN8710 is currently not always working correctly, >> therefore this small change was proposed. Should we really change all >> PHY/FECs only because of this? >> Furthermore one problem still remains: The enet_refclk is controlled by the >> FEC. How does the PHY recognize when it was disabled/enabled? >> > Your patch is workaround for the issue. As you pointed out these is a common issue. > So we hope to get a better solution to handle these in common code. Ok. I'm fine with moving the phy-reset-gpios binding into the PHY. But one question still remains: Who should then trigger the "hard reset" of the PHY? The PHY itself doesn't "know" when the refclk is turned off/on. So the FEC still must call some function of the PHY after the clock was enabled again. So the phy-reset-after-clk-enable property will remain in the fec node? Or am I missing something?