Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752200AbdGIMZ1 (ORCPT ); Sun, 9 Jul 2017 08:25:27 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:34633 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751774AbdGIMZZ (ORCPT ); Sun, 9 Jul 2017 08:25:25 -0400 MIME-Version: 1.0 In-Reply-To: <65066c74b8dedfeb8de27d90b5fecfea3a700178.1499197129.git-series.plaes@plaes.org> References: <65066c74b8dedfeb8de27d90b5fecfea3a700178.1499197129.git-series.plaes@plaes.org> From: Jonathan Liu Date: Sun, 9 Jul 2017 22:25:23 +1000 Message-ID: Subject: Re: [PATCH v5 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver To: Priit Laes Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Russell King , Philipp Zabel , linux-clk@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1613 Lines: 40 Hi Priit, On 5 July 2017 at 06:04, Priit Laes wrote: > Introduce a clock controller driver for sun4i A10 and sun7i A20 > series SoCs. > > Signed-off-by: Priit Laes > --- > drivers/clk/sunxi-ng/Kconfig | 14 +- > drivers/clk/sunxi-ng/Makefile | 1 +- > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 1448 ++++++++++++++++++++++- > drivers/clk/sunxi-ng/ccu-sun4i-a10.h | 61 +- > include/dt-bindings/clock/sun4i-a10-ccu.h | 200 +++- > include/dt-bindings/clock/sun7i-a20-ccu.h | 53 +- > include/dt-bindings/reset/sun4i-a10-ccu.h | 67 +- > 7 files changed, 1844 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h > create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h > create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h > create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h > [snip] > diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c > new file mode 100644 > index 0000000..49052b7 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c [snip] > +static const char *const hdmi_parents[] = { "pll-video0", "pll-video0-2x", > + "pll-video1", "pll-video1-2x" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, > + 0x150, 0, 4, 24, 2, BIT(31), 0); hdmi_parents is in the wrong order. The correct order is "pll-video0", "pll-video1", "pll-video0-2x", "pll-video1-2x". Regards, Jonathan