Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754306AbdGJPAu (ORCPT ); Mon, 10 Jul 2017 11:00:50 -0400 Received: from pegasos-out.vodafone.de ([80.84.1.38]:54257 "EHLO pegasos-out.vodafone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754085AbdGJPAG (ORCPT ); Mon, 10 Jul 2017 11:00:06 -0400 X-Spam-Flag: NO X-Spam-Score: 0.2 Authentication-Results: rohrpostix1.prod.vfnet.de (amavisd-new); dkim=pass header.i=@vodafone.de X-DKIM: OpenDKIM Filter v2.6.8 pegasos-out.vodafone.de C890F2621E9 From: =?UTF-8?q?Christian=20K=C3=B6nig?= To: helgaas@kernel.org, linux-pci@vger.kernel.org, dri-devel@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org Subject: [PATCH v8 4/6] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 30h-3fh) Processors v4 Date: Mon, 10 Jul 2017 16:59:52 +0200 Message-Id: <1499698794-1718-5-git-send-email-deathsimple@vodafone.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499698794-1718-1-git-send-email-deathsimple@vodafone.de> References: <1499698794-1718-1-git-send-email-deathsimple@vodafone.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3667 Lines: 105 From: Christian König Most BIOS don't enable this because of compatibility reasons. Manually enable a 64bit BAR of 64GB size so that we have enough room for PCI devices. v2: style cleanups, increase size, add resource name, set correct flags, print message that windows was added v3: add defines for all the magic numbers, style cleanups v4: add some comment that the BIOS should actually allow this using _PRS and _SRS. Signed-off-by: Christian König Reviewed-by: Andy Shevchenko --- arch/x86/pci/fixup.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 11e4074..0f4088b 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -618,3 +618,79 @@ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); + +#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) +#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) +#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) +#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) + +#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) +#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) + +#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) +#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) + +/* + * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow + * configuring host bridge windows using the _PRS and _SRS methods. + * + * But this is rarely implemented, so we manually enable a large 64bit BAR for + * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. + */ +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) +{ + struct resource *res, *conflict; + u32 base, limit, high; + unsigned i; + + for (i = 0; i < 8; ++i) { + pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); + pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); + + /* Is this slot free? */ + if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | + AMD_141b_MMIO_BASE_WE_MASK))) + break; + + base >>= 8; + base |= high << 24; + + /* Abort if a slot already configures a 64bit BAR. */ + if (base > 0x10000) + return; + } + if (i == 8) + return; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + return; + + res->name = "PCI Bus 0000:00"; + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; + res->start = 0x100000000ull; + res->end = 0xfd00000000ull - 1; + + /* Just grab the free area behind system memory for this */ + while ((conflict = request_resource_conflict(&iomem_resource, res))) + res->start = conflict->end + 1; + + dev_info(&dev->dev, "adding root bus resource %pR\n", res); + + base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | + AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; + limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; + high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | + ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) + & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); + + pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); + pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); + pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); + + pci_bus_add_resource(dev->bus, res, 0); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); -- 2.7.4