Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933739AbdGKQOT (ORCPT ); Tue, 11 Jul 2017 12:14:19 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:51842 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932758AbdGKQOR (ORCPT ); Tue, 11 Jul 2017 12:14:17 -0400 From: Fabrice Gasnier To: , CC: , , , , , , Subject: [PATCH 1/2] ARM: dts: stm32: add ADC support on stm32h7 Date: Tue, 11 Jul 2017 18:13:09 +0200 Message-ID: <1499789590-13021-2-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499789590-13021-1-git-send-email-fabrice.gasnier@st.com> References: <1499789590-13021-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG8NODE3.st.com (10.75.127.24) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-07-11_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1846 Lines: 76 Add support for ADC (Analog to Digital Converter) to STM32H7. It has 3 ADCs, distributed over two ADC blocks: - ADC1 and ADC2 @0x40022000 - ADC3 @0x58026000 (instantiated separately) Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/stm32h743.dtsi | 53 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 4685629..bc47119 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -74,6 +74,59 @@ interrupts = <50>; clocks = <&timer_clk>; }; + + adc_12: adc@40022000 { + compatible = "st,stm32h7-adc-core"; + reg = <0x40022000 0x400>; + interrupts = <18>; + clocks = <&timer_clk>; + clock-names = "bus"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc_12>; + interrupts = <0>; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupt-parent = <&adc_12>; + interrupts = <1>; + status = "disabled"; + }; + }; + + adc_3: adc@58026000 { + compatible = "st,stm32h7-adc-core"; + reg = <0x58026000 0x400>; + interrupts = <127>; + clocks = <&timer_clk>; + clock-names = "bus"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc3: adc@0 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc_3>; + interrupts = <0>; + status = "disabled"; + }; + }; }; }; -- 1.9.1