Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932313AbdGLKIq (ORCPT ); Wed, 12 Jul 2017 06:08:46 -0400 Received: from pegase1.c-s.fr ([93.17.236.30]:33022 "EHLO pegase1.c-s.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750959AbdGLKIp (ORCPT ); Wed, 12 Jul 2017 06:08:45 -0400 Message-Id: From: Christophe Leroy Subject: [PATCH 0/7] Prepare 8xx for CONFIG_STRICT_KERNEL_RWX To: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Scott Wood Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: Wed, 12 Jul 2017 12:08:43 +0200 (CEST) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 850 Lines: 22 This serie makes the PINning of ITLBs optional in the 8xx in order to allow STRICT_KERNEL_RWX to work properly Christophe Leroy (7): powerpc/8xx: Ensures RAM mapped with LTLB is seen as block mapped on 8xx. powerpc/8xx: Remove macro that checks kernel address powerpc/32: Avoid risk of unrecoverable TLBmiss inside entry_32.S powerpc/8xx: Make pinning of ITLBs optional powerpc/8xx: Do not allow Pinned TLBs with STRICT_KERNEL_RWX or DEBUG_PAGEALLOC powerpc/8xx: mark init functions with __init powerpc/8xx: Reduce DTLB miss handler by one insn arch/powerpc/Kconfig | 13 +++++- arch/powerpc/kernel/entry_32.S | 7 +++ arch/powerpc/kernel/head_8xx.S | 96 +++++++++++++++++++++++++++++------------- arch/powerpc/mm/8xx_mmu.c | 29 ++++++++++--- 4 files changed, 107 insertions(+), 38 deletions(-) -- 2.12.0