Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752608AbdGMOOP (ORCPT ); Thu, 13 Jul 2017 10:14:15 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:58937 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752371AbdGMONV (ORCPT ); Thu, 13 Jul 2017 10:13:21 -0400 From: Maxime Ripard To: Mark Brown , Thierry Reding , Laurent Pinchart , Chen-Yu Tsai , Maxime Ripard Cc: dri-devel@lists.freedesktop.org, Daniel Vetter , David Airlie , Mark Rutland , Rob Herring , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Boris Brezillon , Thomas Petazzoni Subject: [PATCH 09/18] drm/sun4i: tcon: Adjust dotclock dividers range Date: Thu, 13 Jul 2017 16:13:04 +0200 Message-Id: <74db696da66cffafe1e729fe2df73b437c8fd483.1499955058.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1519 Lines: 41 It seems like the dotclock dividers are a bit less strict range, and can operate even with a smaller than 6 divider. Loose the boundaries a bit. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c index d401156490f3..0b844c0dd102 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c @@ -77,7 +77,25 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate, u8 best_div = 1; int i; - for (i = 6; i <= 127; i++) { + /* + * There's something odd here. + * + * In the A13 user manual, this is stated to be >= 6 when + * dclk1 and dclk2 are used (without any hint on how to use + * them), and >= 4 when only dclk is used. + * + * In the A33 user manual, when only dclk is used, it is set + * to be >= 6 in the former case, and >= 1 in the + * latter. There's also some (obscure) explanations about the + * dclk1 and dclk2 vs dclk that seems to be in the upper 4 + * bits. What those clocks are and what bit does what is not + * really clear. + * + * On the A33 however, while something lower than 4 works, it + * does have a few artifacts. Let's not use those values, and + * see how it goes. + */ + for (i = 4; i <= 127; i++) { unsigned long ideal = rate * i; unsigned long rounded; -- git-series 0.9.1