Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754232AbdGNNyx (ORCPT ); Fri, 14 Jul 2017 09:54:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37402 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753599AbdGNNyv (ORCPT ); Fri, 14 Jul 2017 09:54:51 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4AEE0602A8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org Subject: Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported To: Ding Tianhong , leedom@chelsio.com, ashok.raj@intel.com, bhelgaas@google.com, helgaas@kernel.org, werner@chelsio.com, ganeshgr@chelsio.com, asit.k.mallick@intel.com, patrick.j.cramer@intel.com, Suravee.Suthikulpanit@amd.com, Bob.Shaw@amd.com, l.stach@pengutronix.de, amira@mellanox.com, gabriele.paoloni@huawei.com, David.Laight@aculab.com, jeffrey.t.kirsher@intel.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, davem@davemloft.net, alexander.duyck@gmail.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linuxarm@huawei.com References: <1499955692-26556-1-git-send-email-dingtianhong@huawei.com> <1499955692-26556-3-git-send-email-dingtianhong@huawei.com> <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> From: Sinan Kaya Message-ID: <67be791f-e0cf-8284-9229-17174dc741ef@codeaurora.org> Date: Fri, 14 Jul 2017 09:54:45 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 711 Lines: 14 On 7/13/2017 9:26 PM, Ding Tianhong wrote: > There is no code to enable the PCIe Relaxed Ordering bit in the configuration space, > it is only be enable by default according to the PCIe Standard Specification, what we > do is to distinguish the RC problematic platform and clear the Relaxed Ordering bit > to tell the PCIe EP don't send any TLPs with Relaxed Ordering Attributes to the Root > Complex. Maybe, you should change the patch commit as "Disable PCIe Relaxed Ordering if not supported"... -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.