Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751367AbdGQRQM (ORCPT ); Mon, 17 Jul 2017 13:16:12 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:32768 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751291AbdGQRQK (ORCPT ); Mon, 17 Jul 2017 13:16:10 -0400 Date: Mon, 17 Jul 2017 10:16:08 -0700 From: Matthias Kaehlcke To: Jani Nikula , Daniel Vetter , intel-gfx , Linux Kernel Mailing List , dri-devel@lists.freedesktop.org, =?utf-8?B?U3TDqXBoYW5l?= Marchesin , Grant Grundler Subject: Re: [PATCH] drm/i915: Consistently use enum pipe for PCH transcoders Message-ID: <20170717171608.GL95735@google.com> References: <20170715010403.180622-1-mka@chromium.org> <20170717090701.yuefohdzqtngx27x@phenom.ffwll.local> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20170717090701.yuefohdzqtngx27x@phenom.ffwll.local> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 9664 Lines: 211 El Mon, Jul 17, 2017 at 11:07:01AM +0200 Daniel Vetter ha dit: > On Fri, Jul 14, 2017 at 06:04:03PM -0700, Matthias Kaehlcke wrote: > > The current code uses two different enum types for PCH transcoders and > > performs implicit conversions between the two types. This is error prone > > and causes clang to raise warnings like this: > > > > drivers/gpu/drm/i915/intel_dp.c:3546:51: warning: implicit conversion > > from enumeration type 'enum pipe' to different enumeration type > > 'enum transcoder' [-Wenum-conversion] > > intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); > > > > Consistently use the type enum pipe for PCH transcoders. > > > > Signed-off-by: Matthias Kaehlcke > > Thanks for respinning. Unfortunately it doesn't apply cleanly to > drm-intel-next-queued, and I don't have a clang setup ready to confirm I > didn't screw up anything. Can you pls rebase? Thanks for having a look. The patch was against v4.12, I will rebase it on drm-intel-next-queued. > > --- > > drivers/gpu/drm/i915/i915_irq.c | 10 +++++----- > > drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++-------------- > > drivers/gpu/drm/i915/intel_drv.h | 6 +++--- > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +++--- > > 4 files changed, 21 insertions(+), 25 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 190f6aa5d15e..7960d2170750 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -2132,10 +2132,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > > DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); > > > > if (pch_iir & SDE_TRANSA_FIFO_UNDER) > > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); > > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); > > > > if (pch_iir & SDE_TRANSB_FIFO_UNDER) > > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); > > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); > > } > > > > static void ivb_err_int_handler(struct drm_i915_private *dev_priv) > > @@ -2169,13 +2169,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) > > DRM_ERROR("PCH poison interrupt\n"); > > > > if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) > > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); > > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); > > > > if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) > > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); > > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); > > > > if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) > > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); > > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C); > > > > I915_WRITE(SERR_INT, serr_int); > > } > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 9106ea32b048..21a8fea46ad9 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -1782,7 +1782,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, > > > > /* FDI must be feeding us bits for PCH ports */ > > assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); > > - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); > > + assert_fdi_rx_enabled(dev_priv, PIPE_A); > > > > /* Workaround: set timing override bit. */ > > val = I915_READ(TRANS_CHICKEN2(PIPE_A)); > > @@ -1858,16 +1858,16 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) > > I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); > > } > > > > -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) > > +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) > > { > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > WARN_ON(!crtc->config->has_pch_encoder); > > > > if (HAS_PCH_LPT(dev_priv)) > > - return TRANSCODER_A; > > + return PIPE_A; > > else > > - return (enum transcoder) crtc->pipe; > > + return crtc->pipe; > > } > > > > /** > > @@ -1906,7 +1906,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > > if (crtc->config->has_pch_encoder) { > > /* if driving the PCH, we need FDI enabled */ > > assert_fdi_rx_pll_enabled(dev_priv, > > - (enum pipe) intel_crtc_pch_transcoder(crtc)); > > + intel_crtc_pch_transcoder(crtc)); > > assert_fdi_tx_pll_enabled(dev_priv, > > (enum pipe) cpu_transcoder); > > } > > @@ -4573,7 +4573,7 @@ static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > > > - assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); > > + assert_pch_transcoder_disabled(dev_priv, PIPE_A); > > > > lpt_program_iclkip(crtc); > > > > @@ -5329,8 +5329,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > > return; > > > > if (intel_crtc->config->has_pch_encoder) > > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > > - false); > > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); > > > > intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); > > > > @@ -5415,8 +5414,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > > intel_wait_for_vblank(dev_priv, pipe); > > intel_wait_for_vblank(dev_priv, pipe); > > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > > - true); > > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); > > } > > > > /* If we change the relative order between pipe/planes enabling, we need > > @@ -5513,8 +5511,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, > > enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > > > > if (intel_crtc->config->has_pch_encoder) > > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > > - false); > > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); > > > > intel_encoders_disable(crtc, old_crtc_state, old_state); > > > > @@ -5542,8 +5539,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, > > intel_encoders_post_disable(crtc, old_crtc_state, old_state); > > > > if (old_crtc_state->has_pch_encoder) > > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > > - true); > > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); > > } > > > > static void i9xx_pfit_enable(struct intel_crtc *crtc) > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index f630c7af5020..d337ca88faed 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -1169,12 +1169,12 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) > > bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > > enum pipe pipe, bool enable); > > bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > > - enum transcoder pch_transcoder, > > + enum pipe pch_transcoder, > > bool enable); > > void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > > enum pipe pipe); > > void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > > - enum transcoder pch_transcoder); > > + enum pipe pch_transcoder); > > void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); > > void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); > > > > @@ -1280,7 +1280,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, > > const struct intel_cdclk_state *cdclk_state); > > > > /* intel_display.c */ > > -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); > > +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); > > void intel_update_rawclk(struct drm_i915_private *dev_priv); > > int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); > > int vlv_get_cck_clock(struct drm_i915_private *dev_priv, > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > index 966e255ca053..6c4054de4fda 100644 > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > @@ -313,11 +313,11 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > > * Returns the previous state of underrun reporting. > > */ > > bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > > - enum transcoder pch_transcoder, > > + enum pipe pch_transcoder, > > bool enable) > > { > > struct intel_crtc *crtc = > > - intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder); > > + intel_get_crtc_for_pipe(dev_priv, pch_transcoder); > > unsigned long flags; > > bool old; > > > > @@ -390,7 +390,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > > * interrupt to avoid an irq storm. > > */ > > void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > > - enum transcoder pch_transcoder) > > + enum pipe pch_transcoder) > > { > > if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, > > false)) { >