Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751357AbdGQSlx (ORCPT ); Mon, 17 Jul 2017 14:41:53 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:34408 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751314AbdGQSlv (ORCPT ); Mon, 17 Jul 2017 14:41:51 -0400 Date: Mon, 17 Jul 2017 13:41:49 -0500 From: Rob Herring To: Maxime Ripard Cc: Mark Brown , Thierry Reding , Laurent Pinchart , Chen-Yu Tsai , dri-devel@lists.freedesktop.org, Daniel Vetter , David Airlie , Mark Rutland , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Boris Brezillon , Thomas Petazzoni Subject: Re: [PATCH 11/18] dt-bindings: display: Add Allwinner MIPI-DSI bindings Message-ID: <20170717184149.sv4xdspjwnhmctog@rob-hp-laptop> References: <41dca303c02faf350e765b81c36ddcddbba6f950.1499955058.git-series.maxime.ripard@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <41dca303c02faf350e765b81c36ddcddbba6f950.1499955058.git-series.maxime.ripard@free-electrons.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3397 Lines: 122 On Thu, Jul 13, 2017 at 04:13:06PM +0200, Maxime Ripard wrote: > The Allwinner SoCs usually come with a DSI encoder. Add a binding for it. > > Signed-off-by: Maxime Ripard > --- > Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85 +++++++- > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt > > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt > new file mode 100644 > index 000000000000..2e7c5aa7020f > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt > @@ -0,0 +1,85 @@ > +Allwinner A31 DSI Encoder > +========================= > + > +The DSI pipeline consists of two separate blocks: the DSI controller > +itself, and its associated D-PHY. > + > +DSI Encoder > +----------- > + > +The DSI Encoder generates the DSI signal from the TCON's. > + > +Required properties: > + - compatible: value must be one of: > + * allwinner,sun6i-a31-mipi-dsi > + - reg: base address and size of memory-mapped region > + - interrupts: interrupt associated to this IP > + - clocks: phandles to the clocks feeding the DSI encoder > + * bus: the DSI interface clock > + * mod: the DSI module clock > + - clock-names: the clock names mentioned above > + - phys: phandle to the D-PHY > + - phy-names: must be "dphy" > + - resets: phandle to the reset controller driving the encoder > + > + - ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + port should be the input endpoint, usually coming from the > + associated TCON. Output port for bridge/panel? > + > +D-PHY > +----- > + > +Required properties: > + - compatible: value must be one of: > + * allwinner,sun6i-a31-mipi-dphy > + - reg: base address and size of memory-mapped region > + - clocks: phandles to the clocks feeding the DSI encoder > + * bus: the DSI interface clock > + * mod: the DSI module clock > + - clock-names: the clock names mentioned above > + - resets: phandle to the reset controller driving the encoder > + > +Example: > + > +dsi0: dsi@01ca0000 { Drop the leading 0. > + compatible = "allwinner,sun6i-a31-mipi-dsi"; > + reg = <0x01ca0000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_MIPI_DSI>, > + <&ccu CLK_DSI_SCLK>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_MIPI_DSI>; > + phys = <&dphy0>; > + phy-names = "dphy"; > + #address-cells = <1>; > + #size-cells = <0>; Not needed. > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + dsi0_in: port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + dsi0_in_tcon0: endpoint@0 { > + reg = <0>; Don't need reg when there's only 1 endpoint. > + remote-endpoint = <&tcon0_out_dsi0>; > + }; > + }; > + }; > +}; > + > +dphy0: d-phy@01ca1000 { Drop leading 0. > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > + reg = <0x01ca1000 0x1000>; > + clocks = <&ccu CLK_BUS_MIPI_DSI>, > + <&ccu CLK_DSI_DPHY>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_MIPI_DSI>; > + #address-cells = <1>; > + #size-cells = <0>; For what? > + #phy-cells = <0>; > +}; > -- > git-series 0.9.1