Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751457AbdGQT0M (ORCPT ); Mon, 17 Jul 2017 15:26:12 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:42028 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751433AbdGQT0I (ORCPT ); Mon, 17 Jul 2017 15:26:08 -0400 From: Christopher Bostic To: wim@iguana.be, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com, joel@jms.id.au, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org Cc: Christopher Bostic , linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v5 2/2] drivers/watchdog: ASPEED reference dev tree properties for config Date: Mon, 17 Jul 2017 14:25:39 -0500 X-Mailer: git-send-email 2.10.1 (Apple Git-78) In-Reply-To: <20170717192539.7950-1-cbostic@linux.vnet.ibm.com> References: <20170717192539.7950-1-cbostic@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17071719-0016-0000-0000-00000731D1AA X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007379; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000214; SDB=6.00888981; UDB=6.00444004; IPR=6.00669153; BA=6.00005476; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016251; XFM=3.00000015; UTC=2017-07-17 19:26:06 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17071719-0017-0000-0000-00003AA06D6F Message-Id: <20170717192539.7950-3-cbostic@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-07-17_15:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1706020000 definitions=main-1707170311 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3657 Lines: 96 Reference the system device tree when configuring the watchdog engines. If property 'aspeed,reset_type' is present then set reset behavior based on the specified value. This can be one of three different mutually exclusive values * cpu - Reset CPU only on watchdog timeout * soc - Reset System on Chip * system - Full system reset No reset can also be specified by indicating: * none - No reset, assumes another watchdog is responsible for this. Add optional property 'aspeed,external-signal'. If present then configure to generate external signal on watchdog timeout. Signed-off-by: Christopher Bostic --- v5 - Add explicit check for property type "none". Return error if property type is not a known value. - Default reset type when no property present changed to match original code: SOC + SYSTEM reset v4 - Change the three reset type parameters to a new property 'aspeed,reset_type' and check assignment for one of four different values, cpu, soc, system, none v3 - Invert the logic for system reset dev tree property to preserve backwards compatibility. If not specified the default is to configure for system reset - Add check for 'aspeed,no-soc-reset' property and only if not present is SOC reset to be configured. This preserves backwards compatibility. v2 - Change of_get_property() to of_property_read_bool() - Remove redundant check for NULL struct device_node pointer - Optional property names now start with prefix 'aspeed,' --- drivers/watchdog/aspeed_wdt.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index 1c65258..c707ab6 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -36,6 +36,7 @@ struct aspeed_wdt { #define WDT_CTRL 0x0C #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) #define WDT_CTRL_1MHZ_CLK BIT(4) #define WDT_CTRL_WDT_EXT BIT(3) #define WDT_CTRL_WDT_INTR BIT(2) @@ -140,6 +141,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev) { struct aspeed_wdt *wdt; struct resource *res; + struct device_node *np; + const char *reset_type; int ret; wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); @@ -164,14 +167,30 @@ static int aspeed_wdt_probe(struct platform_device *pdev) wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev); + wdt->ctrl = WDT_CTRL_1MHZ_CLK; + /* * Control reset on a per-device basis to ensure the - * host is not affected by a BMC reboot, so only reset - * the SOC and not the full chip + * host is not affected by a BMC reboot */ - wdt->ctrl = WDT_CTRL_RESET_MODE_SOC | - WDT_CTRL_1MHZ_CLK | - WDT_CTRL_RESET_SYSTEM; + np = pdev->dev.of_node; + ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); + if (ret) { + wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; + } else { + if (!strcmp(reset_type, "cpu")) + wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU; + else if (!strcmp(reset_type, "soc")) + wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC; + else if (!strcmp(reset_type, "system")) + wdt->ctrl |= WDT_CTRL_RESET_SYSTEM; + else if (strcmp(reset_type, "none")) + return -EINVAL; + } + if (of_property_read_bool(np, "aspeed,external-signal")) + wdt->ctrl |= WDT_CTRL_WDT_EXT; + + writel(wdt->ctrl, wdt->base + WDT_CTRL); if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { aspeed_wdt_start(&wdt->wdd); -- 1.8.2.2