Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752129AbdGRBSB (ORCPT ); Mon, 17 Jul 2017 21:18:01 -0400 Received: from mga04.intel.com ([192.55.52.120]:28986 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751530AbdGRBR6 (ORCPT ); Mon, 17 Jul 2017 21:17:58 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,376,1496127600"; d="scan'208";a="112438316" From: "Wu, Hao" To: Alan Tull CC: Moritz Fischer , "linux-fpga@vger.kernel.org" , linux-kernel , "linux-api@vger.kernel.org" , "Kang, Luwei" , "Zhang, Yi Z" , "Whisonant, Tim" , "Luebbers, Enno" , "Rao, Shiva" , "Rauer, Christopher" , Xiao Guangrong Subject: RE: [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Thread-Topic: [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Thread-Index: AQHS/y4j0S82JXPszEGziww7vPP8TaJYv6lQ Date: Tue, 18 Jul 2017 01:17:52 +0000 Message-ID: References: <1498441938-14046-1-git-send-email-hao.wu@intel.com> <1498441938-14046-13-git-send-email-hao.wu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v6I1I4Pk022301 Content-Length: 3686 Lines: 103 > On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao wrote: > > Hi Hao, > > I'm making my way through this (very large) patchset. Some minor > comments below. > Hi Alan Thanks for your review. : ) > > From: Kang Luwei > > > > The header register set is always present for FPGA Management Engine (FME), > > this patch implements init and uinit function for header sub feature and > > introduce several read-only sysfs interfaces for the capability and status. > > > > Sysfs interfaces: > > * /sys/class/fpga///ports_num > > Read-only. Number of ports implemented > > > > * /sys/class/fpga///bitstream_id > > Read-only. Blue Bitstream identifier number > > Blue and Green bitstreams are an Intel implementation terminology. I > see that you've defined them in drivers/fpga, but it will be helpful > to add in "static region" and "partial reconfiguration region" added > in any API documentation files that use the green/blue terminology to > keep it accessible. > Sure, thanks for your suggestion, will update it like this. * /sys/class/fpga///bitstream_id Read-only. Blue Bitstream (static FPGA region) identifier number * /sys/class/fpga///bitstream_metadata Read-only. Blue Bitstream (static FPGA region) meta data > > > > Signed-off-by: Tim Whisonant > > Signed-off-by: Enno Luebbers > > Signed-off-by: Shiva Rao > > Signed-off-by: Christopher Rauer > > Signed-off-by: Kang Luwei > > Signed-off-by: Xiao Guangrong > > Signed-off-by: Wu Hao > > --- > > v2: add sysfs documentation > > --- > > .../ABI/testing/sysfs-platform-intel-fpga-fme | 19 ++++++++ > > drivers/fpga/intel-feature-dev.h | 3 ++ > > drivers/fpga/intel-fme-main.c | 55 ++++++++++++++++++++++ > > 3 files changed, 77 insertions(+) > > create mode 100644 Documentation/ABI/testing/sysfs-platform-intel-fpga- > fme > > > > diff --git a/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme > b/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme > > new file mode 100644 > > index 0000000..783cfa9 > > --- /dev/null > > +++ b/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme > > @@ -0,0 +1,19 @@ > > +What: /sys/bus/platform/devices/intel-fpga-fme.0/ports_num > > +Date: June 2017 > > +KernelVersion: 4.12 > > +Contact: Wu Hao > > +Description: Read-only. One Intel FPGA device may have more than 1 > > + port/Accelerator Function Unit (AFU). It returns the > > + number of ports on the FPGA device when read it. > > + > > +What: /sys/bus/platform/devices/intel-fpga-fme.0/bitstream_id > > +Date: June 2017 > > +KernelVersion: 4.12 > > +Contact: Wu Hao > > +Description: Read-only. It returns Blue Bitstream identifier number. > > Here Will update this patch as below. +Description: Read-only. It returns Blue Bitstream (static FPGA region) + identifier number. > > > + > > +What: /sys/bus/platform/devices/intel-fpga-fme.0/bitstream_meta > > +Date: June 2017 > > +KernelVersion: 4.12 > > +Contact: Wu Hao > > +Description: Read-only. It returns Blue Bitstream meta data. > > And here Will update this patch as below. +Description: Read-only. It returns Blue Bitstream (static FPGA region) + meta data. Thanks Hao