Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751428AbdGRGj6 (ORCPT ); Tue, 18 Jul 2017 02:39:58 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:35904 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751334AbdGRGj4 (ORCPT ); Tue, 18 Jul 2017 02:39:56 -0400 Date: Tue, 18 Jul 2017 08:39:50 +0200 From: Daniel Vetter To: Matthias Kaehlcke Cc: Daniel Vetter , Jani Nikula , Daniel Vetter , intel-gfx , Linux Kernel Mailing List , dri-devel@lists.freedesktop.org, =?iso-8859-1?Q?St=E9phane?= Marchesin , Grant Grundler Subject: Re: [PATCH v2] drm/i915: Consistently use enum pipe for PCH transcoders Message-ID: <20170718063950.ixnm6hevtgoalx4g@phenom.ffwll.local> Mail-Followup-To: Matthias Kaehlcke , Jani Nikula , Daniel Vetter , intel-gfx , Linux Kernel Mailing List , dri-devel@lists.freedesktop.org, =?iso-8859-1?Q?St=E9phane?= Marchesin , Grant Grundler References: <20170717181403.57324-1-mka@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170717181403.57324-1-mka@chromium.org> X-Operating-System: Linux phenom 4.11.0-1-amd64 User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 9307 Lines: 216 On Mon, Jul 17, 2017 at 11:14:03AM -0700, Matthias Kaehlcke wrote: > The current code uses in some instances enum transcoder for PCH > transcoders and enum pipe in others. This is error prone and clang > raises warnings like this: > > drivers/gpu/drm/i915/intel_dp.c:3546:51: warning: implicit conversion > from enumeration type 'enum pipe' to different enumeration type > 'enum transcoder' [-Wenum-conversion] > intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); > > Consistently use the type enum pipe for PCH transcoders. > > Signed-off-by: Matthias Kaehlcke Somehow git apply-mbox could parse it, but manually applying using patch worked. Not sure what's going on, maybe double-check it's all right. Thanks, Daniel > --- > Changes in v2: > - rebased on drm-intel/drm-intel-next-queued > > drivers/gpu/drm/i915/i915_irq.c | 10 +++++----- > drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++-------------- > drivers/gpu/drm/i915/intel_drv.h | 6 +++--- > drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +++--- > 4 files changed, 21 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 1d33cea01a1b..0b6f310101ee 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2086,10 +2086,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); > > if (pch_iir & SDE_TRANSA_FIFO_UNDER) > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); > > if (pch_iir & SDE_TRANSB_FIFO_UNDER) > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); > } > > static void ivb_err_int_handler(struct drm_i915_private *dev_priv) > @@ -2123,13 +2123,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) > DRM_ERROR("PCH poison interrupt\n"); > > if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); > > if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); > > if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) > - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); > + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C); > > I915_WRITE(SERR_INT, serr_int); > } > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index bb9c9c3c391f..5c7054c3be0e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1777,7 +1777,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, > > /* FDI must be feeding us bits for PCH ports */ > assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); > - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); > + assert_fdi_rx_enabled(dev_priv, PIPE_A); > > /* Workaround: set timing override bit. */ > val = I915_READ(TRANS_CHICKEN2(PIPE_A)); > @@ -1853,16 +1853,16 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) > I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); > } > > -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) > +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > WARN_ON(!crtc->config->has_pch_encoder); > > if (HAS_PCH_LPT(dev_priv)) > - return TRANSCODER_A; > + return PIPE_A; > else > - return (enum transcoder) crtc->pipe; > + return crtc->pipe; > } > > /** > @@ -1901,7 +1901,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > if (crtc->config->has_pch_encoder) { > /* if driving the PCH, we need FDI enabled */ > assert_fdi_rx_pll_enabled(dev_priv, > - (enum pipe) intel_crtc_pch_transcoder(crtc)); > + intel_crtc_pch_transcoder(crtc)); > assert_fdi_tx_pll_enabled(dev_priv, > (enum pipe) cpu_transcoder); > } > @@ -4579,7 +4579,7 @@ static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > - assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); > + assert_pch_transcoder_disabled(dev_priv, PIPE_A); > > lpt_program_iclkip(crtc); > > @ -5347,8 +5347,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > return; > > if (intel_crtc->config->has_pch_encoder) > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > - false); > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); > > intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); > > @@ -5433,8 +5432,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > intel_wait_for_vblank(dev_priv, pipe); > intel_wait_for_vblank(dev_priv, pipe); > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > - true); > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); > } > > /* If we change the relative order between pipe/planes enabling, we need > @@ -5531,8 +5529,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, > enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; > > if (intel_crtc->config->has_pch_encoder) > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > - false); > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); > > intel_encoders_disable(crtc, old_crtc_state, old_state); > > @@ -5560,8 +5557,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, > intel_encoders_post_disable(crtc, old_crtc_state, old_state); > > if (old_crtc_state->has_pch_encoder) > - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, > - true); > + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); > } > > static void i9xx_pfit_enable(struct intel_crtc *crtc) > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index d17a32437f07..0902d7cb48d9 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1211,12 +1211,12 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) > bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > enum pipe pipe, bool enable); > bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > - enum transcoder pch_transcoder, > + enum pipe pch_transcoder, > bool enable); > void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > enum pipe pipe); > void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > - enum transcoder pch_transcoder); > + enum pipe pch_transcoder); > void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); > void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); > > @@ -1326,7 +1326,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, > /* intel_display.c */ > void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); > void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); > -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); > +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); > void intel_update_rawclk(struct drm_i915_private *dev_priv); > int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); > int vlv_get_cck_clock(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > index d484862cc7df..5a7cca32c0fa 100644 > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > @@ -313,11 +313,11 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > * Returns the previous state of underrun reporting. > */ > bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, > - enum transcoder pch_transcoder, > + enum pipe pch_transcoder, > bool enable) > { > struct intel_crtc *crtc = > - intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder); > + intel_get_crtc_for_pipe(dev_priv, pch_transcoder); > unsigned long flags; > bool old; > > @@ -390,7 +390,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > * interrupt to avoid an irq storm. > */ > void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, > - enum transcoder pch_transcoder) > + enum pipe pch_transcoder) > { > if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, > false)) { > -- > 2.13.2.932.g7449e964c-goog > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch