Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751422AbdGRHyg (ORCPT ); Tue, 18 Jul 2017 03:54:36 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:42222 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751203AbdGRHyd (ORCPT ); Tue, 18 Jul 2017 03:54:33 -0400 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , , , Lee Jones , Vladimir Zapolskiy , Sylvain Lemieux CC: , , , , , , , , , Arvind Yadav Subject: [PATCH v6 0/3] clk: stm32h7: Add stm32h743 clock driver Date: Tue, 18 Jul 2017 09:53:31 +0200 Message-ID: <1500364414-10021-1-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-07-18_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2222 Lines: 60 From: Gabriel Fernandez v6: - rename clk_gate_is_enabled() in nxp lpc32xx driver. - add EXPORT_SYMBOL_GPL(clk_gate_is_enabled) v5: - return bool instead int for enable_power_domain_write_protection() - add comment to explain use of CLK_OF_DECLARE_DRIVER() - add comment to explain why we can't use read_poll_timeout() - expose clk_gate_ops::is_enabled - use of __clk_mux_determine_rate & clk_gate_is_enabled to avoid wrapper function. v4: - rename lock into stm32rcc_lock - don't use clk_readl() - remove useless parentheses with GENMASK - fix parents of timer_x clocks - suppress pll configuration from DT - fix kbuild warning v3: - fix compatible string "stm32h7-pll" into "st,stm32h7-pll" - fix bad parent name for mco2 clock - set CLK_SET_RATE_PARENT for ltdc clock - set CLK_IGNORE_UNUSED for pll1 - disable power domain write protection on disable ops if needed v2: - rename compatible string "stm32,pll" into "stm32h7-pll" - suppress "st,pllrge" property - suppress "st, frac-status" property - change management of "st,frac" property 0 : enable 0 pll integer mode other values : enable pll in fractional mode (value is the fractional factor) Gabriel Fernandez (3): clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled() clk: gate: expose clk_gate_ops::is_enabled clk: stm32h7: Add stm32h743 clock driver .../devicetree/bindings/clock/st,stm32h7-rcc.txt | 81 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-gate.c | 3 +- drivers/clk/clk-stm32h7.c | 1522 ++++++++++++++++++++ drivers/clk/nxp/clk-lpc32xx.c | 4 +- include/dt-bindings/clock/stm32h7-clks.h | 165 +++ include/dt-bindings/mfd/stm32h7-rcc.h | 136 ++ include/linux/clk-provider.h | 1 + 8 files changed, 1910 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt create mode 100644 drivers/clk/clk-stm32h7.c create mode 100644 include/dt-bindings/clock/stm32h7-clks.h create mode 100644 include/dt-bindings/mfd/stm32h7-rcc.h -- 1.9.1