Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751522AbdGRL1Q (ORCPT ); Tue, 18 Jul 2017 07:27:16 -0400 Received: from mail.izt-labs.de ([82.135.25.162]:50235 "EHLO mail.izt-labs.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751365AbdGRL1M (ORCPT ); Tue, 18 Jul 2017 07:27:12 -0400 From: Johannes Poehlmann To: linux-kernel@vger.kernel.org Cc: Johannes Poehlmann , Evgeniy Polyakov , Greg Kroah-Hartman Subject: [PATCH v3 1/4] w1: ds1wm: fix and simplify register access Date: Tue, 18 Jul 2017 13:26:50 +0200 Message-Id: <1500377213-1117-2-git-send-email-johannes.poehlmann@izt-labs.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1500377213-1117-1-git-send-email-johannes.poehlmann@izt-labs.de> References: <1500377213-1117-1-git-send-email-johannes.poehlmann@izt-labs.de> In-Reply-To: <6a03463f-7e93-8ee7-d56f-aaed1e2befba@izt-labs.de> References: <6a03463f-7e93-8ee7-d56f-aaed1e2befba@izt-labs.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4835 Lines: 163 o Replace incorrect register offsett calculation by direct configuration of bus_shift in mfd-cell. Indirect definition of address-shift by resource size was unobvious and should have used a binary log. o Make endian clean, make HW-endianness configurable. o Use ioread*, iowrite* instead of __raw_readb,__raw_writeb to also use memory-barriers when accessing HW-registers. We do not want reordering to happen here. Signed-off-by: Johannes Poehlmann Acked-by: Evgeniy Polyakov --- drivers/w1/masters/ds1wm.c | 84 ++++++++++++++++++++++++++++++++++++++++++---- include/linux/mfd/ds1wm.h | 9 +++++ 2 files changed, 87 insertions(+), 6 deletions(-) diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c index fd2e9da..6bba2fe 100644 --- a/drivers/w1/masters/ds1wm.c +++ b/drivers/w1/masters/ds1wm.c @@ -95,7 +95,8 @@ static struct { struct ds1wm_data { void __iomem *map; - int bus_shift; /* # of shifts to calc register offsets */ + unsigned int bus_shift; /* # of shifts to calc register offsets */ + int is_hw_big_endian; struct platform_device *pdev; const struct mfd_cell *cell; int irq; @@ -115,12 +116,66 @@ struct ds1wm_data { static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg, u8 val) { - __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift)); + if (ds1wm_data->is_hw_big_endian) { + switch (ds1wm_data->bus_shift) { + case 0: + iowrite8(val, ds1wm_data->map + (reg << 0)); + break; + case 1: + iowrite16be((u16)val, ds1wm_data->map+(reg<<1)); + break; + case 2: + iowrite32be((u32)val, ds1wm_data->map+(reg<<2)); + break; + } + } else { + switch (ds1wm_data->bus_shift) { + case 0: + iowrite8(val, ds1wm_data->map + (reg << 0)); + break; + case 1: + iowrite16((u16) val, ds1wm_data->map+(reg << 1)); + break; + case 2: + iowrite32((u32) val, ds1wm_data->map+(reg << 2)); + break; + } + } } static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg) { - return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift)); + + u32 val = 0; + + if (ds1wm_data->is_hw_big_endian) { + switch (ds1wm_data->bus_shift) { + case 0: + val = ioread8(ds1wm_data->map + (reg << 0)); + break; + case 1: + val = ioread16be(ds1wm_data->map + (reg << 1)); + break; + case 2: + val = ioread32be(ds1wm_data->map + (reg << 2)); + break; + } + } else { + switch (ds1wm_data->bus_shift) { + case 0: + val = ioread8(ds1wm_data->map + (reg << 0)); + break; + case 1: + val = ioread16(ds1wm_data->map + (reg << 1)); + break; + case 2: + val = ioread32(ds1wm_data->map + (reg << 2)); + break; + } + } + dev_dbg(&ds1wm_data->pdev->dev, + "ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val); + return (u8) val; } @@ -473,9 +528,6 @@ static int ds1wm_probe(struct platform_device *pdev) if (!ds1wm_data->map) return -ENOMEM; - /* calculate bus shift from mem resource */ - ds1wm_data->bus_shift = resource_size(res) >> 3; - ds1wm_data->pdev = pdev; ds1wm_data->cell = mfd_get_cell(pdev); if (!ds1wm_data->cell) @@ -484,6 +536,26 @@ static int ds1wm_probe(struct platform_device *pdev) if (!plat) return -ENODEV; + /* how many bits to shift register number to get register offset */ + if (plat->bus_shift > 2) { + dev_err(&ds1wm_data->pdev->dev, + "illegal bus shift %d, not written", + ds1wm_data->bus_shift); + return -EINVAL; + } + + ds1wm_data->bus_shift = plat->bus_shift; + /* make sure resource has space for 8 registers */ + if ((8 << ds1wm_data->bus_shift) > resource_size(res)) { + dev_err(&ds1wm_data->pdev->dev, + "memory resource size %d to small, should be %d\n", + (int) resource_size(res), + 8 << ds1wm_data->bus_shift); + return -EINVAL; + } + + ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res) return -ENXIO; diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h index 38a372a..4efd626 100644 --- a/include/linux/mfd/ds1wm.h +++ b/include/linux/mfd/ds1wm.h @@ -3,6 +3,7 @@ struct ds1wm_driver_data { int active_high; int clock_rate; + /* in milliseconds, the amount of time to */ /* sleep following a reset pulse. Zero */ /* should work if your bus devices recover*/ @@ -10,4 +11,12 @@ struct ds1wm_driver_data { /* ds1wm implements the precise timings of*/ /* a reset pulse/presence detect sequence.*/ unsigned int reset_recover_delay; + + /* Say 1 here for big endian Hardware */ + /* (only relevant with bus-shift > 0 */ + int is_hw_big_endian; + + /* left shift of register number to get register address offsett */ + /* only 0,1,2 allowed for 8,16 or 32 bit bus width respectively */ + unsigned int bus_shift; }; -- 2.1.4