Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754244AbdGSJ4l (ORCPT ); Wed, 19 Jul 2017 05:56:41 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:35600 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753554AbdGSJ4g (ORCPT ); Wed, 19 Jul 2017 05:56:36 -0400 From: Anup Patel To: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Jassi Brar Cc: Florian Fainelli , Scott Branden , Ray Jui , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Anup Patel , stable@vger.kernel.org Subject: [PATCH 3/6] mailbox: bcm-flexrm-mailbox: Fix mask used in CMPL_START_ADDR_VALUE() Date: Wed, 19 Jul 2017 15:25:39 +0530 Message-Id: <1500458142-19243-4-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500458142-19243-1-git-send-email-anup.patel@broadcom.com> References: <1500458142-19243-1-git-send-email-anup.patel@broadcom.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1102 Lines: 32 The mask used in CMPL_START_ADDR_VALUE() should be 27bits instead of 26bits. This incorrect mask was causing completion writes to 40bits physical address fail. This patch fixes mask used in CMPL_START_ADDR_VALUE() macro. Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager") Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Cc: stable@vger.kernel.org --- drivers/mailbox/bcm-flexrm-mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/bcm-flexrm-mailbox.c b/drivers/mailbox/bcm-flexrm-mailbox.c index a0be2ea..46ad305 100644 --- a/drivers/mailbox/bcm-flexrm-mailbox.c +++ b/drivers/mailbox/bcm-flexrm-mailbox.c @@ -97,7 +97,7 @@ /* Register RING_CMPL_START_ADDR fields */ #define CMPL_START_ADDR_VALUE(pa) \ - ((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x03ffffff)) + ((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x07ffffff)) /* Register RING_CONTROL fields */ #define CONTROL_MASK_DISABLE_CONTROL 12 -- 2.7.4