Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933427AbdGSXGD (ORCPT ); Wed, 19 Jul 2017 19:06:03 -0400 Received: from xff.cz ([195.181.215.36]:47638 "EHLO megous.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752045AbdGSXGB (ORCPT ); Wed, 19 Jul 2017 19:06:01 -0400 X-Greylist: delayed 385 seconds by postgrey-1.27 at vger.kernel.org; Wed, 19 Jul 2017 19:06:00 EDT Message-ID: <1500505173.23770.1.camel@xff.cz> Subject: Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu From: =?UTF-8?Q?Ond=C5=99ej?= Jirman To: icenowy@aosc.io, Maxime Ripard , Chen-Yu Tsai Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Date: Thu, 20 Jul 2017 00:59:33 +0200 In-Reply-To: <20170404095100.18649-5-icenowy@aosc.io> References: <20170404095100.18649-1-icenowy@aosc.io> <20170404095100.18649-5-icenowy@aosc.io> Content-Type: multipart/signed; micalg="pgp-sha256"; protocol="application/pgp-signature"; boundary="=-FF0VDUHj64FDp6coUJLd" Mime-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5704 Lines: 171 --=-FF0VDUHj64FDp6coUJLd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, Icenowy Zheng p=C3=AD=C5=A1e v =C3=9At 04. 04. 2017 v 17:50 +0800: > From: Icenowy Zheng >=20 > Now we have driver for the PRCM CCU, switch to use it instead of > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >=20 > The mux 3 of R_CCU is still the internal oscillator, which is said to be > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two > H3 boards and one H5 board. There's issue with the new r_ccu that breaks r_i2c. (no devices can be found on the bus). Reverting this patch fixes the issue with the I2C controller. (everything else being the same)=20 Here's the code I'm using: https://github.com/megous/linux/commits/oran ge-pi-4.12 The last commit is the revert. The issue manifests itself by non-working DVFS, because kernel lacks access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng clock driver (sun8i-r). Relevant difference in registers between working/non-working state is just this (diff -u): 0x01f02400 =3D 0x00000000=20 0x01f02404 =3D 0x00000000=20 -0x01f02408 =3D 0x00000091=20 +0x01f02408 =3D 0x00000095 DATA register inisde the I2C controller 0x01f0240c =3D 0x00000044=20 0x01f02410 =3D 0x000000f8=20 -0x01f02414 =3D 0x00000059=20 +0x01f02414 =3D 0x00000000 CLOCK setup register inside the I2C controller 0x01f02418 =3D 0x00000000=20 0x01f0241c =3D 0x00000000=20 0x01f02420 =3D 0x0000003a=20 It looks like the new sunxi-ng clock driver causes the I2C driver to not correctly configure the CLOCK register. I don't know why and I'm not sure how to deal with this. Any ideas what can I do next? thank you and regards, o. > Signed-off-by: Icenowy Zheng > --- > Changes in v4: > - Temporarily dropped the CCU headers. > Changes in v3: > - Change osc32000 to iosc. >=20 > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++--------------------= ------ > 1 file changed, 14 insertions(+), 31 deletions(-) >=20 > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi= -h3-h5.dtsi > index 6640ebfa6419..1aeeacb3a884 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -68,31 +68,12 @@ > clock-output-names =3D "osc32k"; > }; > =20 > - apb0: apb0_clk { > - compatible =3D "fixed-factor-clock"; > + iosc: internal-osc-clk { > #clock-cells =3D <0>; > - clock-div =3D <1>; > - clock-mult =3D <1>; > - clocks =3D <&osc24M>; > - clock-output-names =3D "apb0"; > - }; > - > - apb0_gates: clk@01f01428 { > - compatible =3D "allwinner,sun8i-h3-apb0-gates-clk", > - "allwinner,sun4i-a10-gates-clk"; > - reg =3D <0x01f01428 0x4>; > - #clock-cells =3D <1>; > - clocks =3D <&apb0>; > - clock-indices =3D <0>, <1>; > - clock-output-names =3D "apb0_pio", "apb0_ir"; > - }; > - > - ir_clk: ir_clk@01f01454 { > - compatible =3D "allwinner,sun4i-a10-mod0-clk"; > - reg =3D <0x01f01454 0x4>; > - #clock-cells =3D <0>; > - clocks =3D <&osc32k>, <&osc24M>; > - clock-output-names =3D "ir"; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <16000000>; > + clock-accuracy =3D <300000000>; > + clock-output-names =3D "iosc"; > }; > }; > =20 > @@ -576,9 +557,12 @@ > ; > }; > =20 > - apb0_reset: reset@01f014b0 { > - reg =3D <0x01f014b0 0x4>; > - compatible =3D "allwinner,sun6i-a31-clock-reset"; > + r_ccu: clock@1f01400 { > + compatible =3D "allwinner,sun50i-a64-r-ccu"; > + reg =3D <0x01f01400 0x100>; > + clocks =3D <&osc24M>, <&osc32k>, <&iosc>; > + clock-names =3D "hosc", "losc", "iosc"; > + #clock-cells =3D <1>; > #reset-cells =3D <1>; > }; > =20 > @@ -589,9 +573,9 @@ > =20 > ir: ir@01f02000 { > compatible =3D "allwinner,sun5i-a13-ir"; > - clocks =3D <&apb0_gates 1>, <&ir_clk>; > + clocks =3D <&r_ccu 4>, <&r_ccu 11>; > clock-names =3D "apb", "ir"; > - resets =3D <&apb0_reset 1>; > + resets =3D <&r_ccu 0>; > interrupts =3D ; > reg =3D <0x01f02000 0x40>; > status =3D "disabled"; > @@ -601,9 +585,8 @@ > compatible =3D "allwinner,sun8i-h3-r-pinctrl"; > reg =3D <0x01f02c00 0x400>; > interrupts =3D ; > - clocks =3D <&apb0_gates 0>, <&osc24M>, <&osc32k>; > + clocks =3D <&r_ccu 3>, <&osc24M>, <&osc32k>; > clock-names =3D "apb", "hosc", "losc"; > - resets =3D <&apb0_reset 0>; > gpio-controller; > #gpio-cells =3D <3>; > interrupt-controller; > --=20 > 2.12.2 >=20 --=-FF0VDUHj64FDp6coUJLd Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQJABAABCAAqFiEEmrE4sgaRYhzUz5ICbmQmxnfP7/EFAllv5FUMHG1lZ2lAeGZm LmN6AAoJEG5kJsZ3z+/xTGYQAJZa/eTjtPQJ2kT2nkrviyEI9EGZ0l04L8BAXGZK kbPEY5Hrk2aSSoL3siTvuWWfwJZS09asGUSLkkQ1fdEnsnrp8stymkLIYJiil1jv M3ksi32wrBt8qP3s+Qv2+ytVObaxXr/eiVRDPDo9600ieS28sLG7otwnjj82U7Px QbKCLdSf45PmyTJRs2QltBLfvVVW7GJaKSDn/wGSFiYxKVq36lURibxJH9NpN9mE qM+mIUzPKU3RxXBoonP9Tee1KL0WWg46Rr3eBlRUi1HMIkmenO9YLqPWc9Z8vfMf q/wWcFlCi+6X2SdyRWw9V5uoeKN4U5mpGmawdlGdH+B5c5oISzv/XNZ+ZLe+0RYt EWjkula3SCxWuKKjBu5HnRbcH/JW9JzOr9kklL8cQeTPwsR3qBKJD6EF9DTke8w9 WnxM5nlCV9PWAKiOCPvvJEefNFVyOebhGsvj8ACcjm33FhHJcIsKHClqo0yTNRO4 uQosY8oRurlD7NIvsndQaYXqRbHGfFAQmJikt/OiLwy+7O2b5A1BZx52iKzbcjfd e2gByuRbuNQA3JpxJnWuHFAx4qfKCtmwHttzLwAaMg8k9PLSvewomJqsnVkGGmXK AWfiI+vOeomZEcBGrCst35Sl4E+iltFKetujmzlyfT6WQrA/3ceElgAQYs21JjRo 3owq =yyRu -----END PGP SIGNATURE----- --=-FF0VDUHj64FDp6coUJLd--