Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936070AbdGTKSr (ORCPT ); Thu, 20 Jul 2017 06:18:47 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:50894 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936001AbdGTKSG (ORCPT ); Thu, 20 Jul 2017 06:18:06 -0400 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, Suzuki K Poulose Subject: [PATCH v5 17/19] coresight tmc: Support for save-restore in ETR Date: Thu, 20 Jul 2017 11:17:27 +0100 Message-Id: <1500545849-23724-18-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1500545849-23724-1-git-send-email-suzuki.poulose@arm.com> References: <1500545849-23724-1-git-send-email-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2803 Lines: 68 The Coresight SoC 600 TMC ETR supports save-restore feature, where the values of the RRP/RWP and STS.Full are retained when it leaves the Disabled state. Hence, we must program the RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP to the base address of the buffer and clear the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 ++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 9 +++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 40ddcf1..68fbc8f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -22,7 +22,7 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { - u32 axictl; + u32 axictl, sts; /* Zero out the memory to help with debug */ memset(drvdata->vaddr, 0, drvdata->size); @@ -47,6 +47,17 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(axictl, drvdata->base + TMC_AXICTL); tmc_write_dba(drvdata, drvdata->paddr); + /* + * If the TMC pointers must be programmed before the session, + * we have to set it properly (i.e, RRP/RWP to base address and + * STS to "not full"). + */ + if (tmc_etr_has_cap(drvdata, TMC_ETR_SAVE_RESTORE)) { + tmc_write_rrp(drvdata, drvdata->paddr); + tmc_write_rwp(drvdata, drvdata->paddr); + sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + } writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index c691014..08f1aea 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -120,6 +120,15 @@ enum tmc_mem_intf_width { #define TMC_ETR_SG (0x1U << 0) /* ETR has separate read/write cache encodings */ #define TMC_ETR_AXI_ARCACHE (0x1U << 1) +/* + * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are + * retained when TMC leaves Disabled state, allowing us to continue + * the tracing from a point where we stopped. This also implies that + * the RRP/RWP/STS.Full should always be programmed to the correct + * value. Unfortunately this is not advertised by the hardware, + * so we have to rely on PID of the IP to detect the functionality. + */ +#define TMC_ETR_SAVE_RESTORE (0x1U << 2) /** * struct tmc_drvdata - specifics associated to an TMC component -- 2.7.5