Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936018AbdGTKSF (ORCPT ); Thu, 20 Jul 2017 06:18:05 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:50874 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936001AbdGTKSC (ORCPT ); Thu, 20 Jul 2017 06:18:02 -0400 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, Suzuki K Poulose Subject: [PATCH v5 13/19] coresight tmc: Detect support for scatter gather Date: Thu, 20 Jul 2017 11:17:23 +0100 Message-Id: <1500545849-23724-14-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1500545849-23724-1-git-send-email-suzuki.poulose@arm.com> References: <1500545849-23724-1-git-send-email-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1797 Lines: 51 The SG unit in the TMC has been removed in Coresight SoC-600. This is however advertised by DEVID:Bit 24 = 0b1. On the previous generation, the bit is RES0, hence we can rely on the DEVID to detect the support. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc.c | 2 ++ drivers/hwtracing/coresight/coresight-tmc.h | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 4e7cd9a..6d9b8e3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -306,6 +306,8 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata, /* Set the unadvertised capabilities */ tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps); + if (!(devid & TMC_DEVID_NOSCAT)) + tmc_etr_set_cap(drvdata, TMC_ETR_SG); /* * ETR configuration uses a 40-bit AXI master in place of * the embedded SRAM of ETB/ETF. diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 7b20863..23dfbf3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -70,6 +70,8 @@ #define TMC_FFCR_STOP_ON_FLUSH BIT(12) +#define TMC_DEVID_NOSCAT BIT(24) + enum tmc_config_type { TMC_CONFIG_TYPE_ETB, TMC_CONFIG_TYPE_ETR, @@ -89,6 +91,9 @@ enum tmc_mem_intf_width { TMC_MEM_INTF_WIDTH_256BITS = 8, }; +/* TMC ETR Capability bit definitions */ +#define TMC_ETR_SG (0x1U << 0) + /** * struct tmc_drvdata - specifics associated to an TMC component * @base: memory mapped base address for this component. -- 2.7.5