Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752562AbdGXDL1 (ORCPT ); Sun, 23 Jul 2017 23:11:27 -0400 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:53178 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751871AbdGXDLU (ORCPT ); Sun, 23 Jul 2017 23:11:20 -0400 MIME-Version: 1.0 In-Reply-To: <20170723102749.17323-7-icenowy@aosc.io> References: <20170723102749.17323-1-icenowy@aosc.io> <20170723102749.17323-7-icenowy@aosc.io> From: Chen-Yu Tsai Date: Mon, 24 Jul 2017 11:10:56 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 To: Icenowy Zheng Cc: Liam Girdwood , Mark Brown , Maxime Ripard , Chen-Yu Tsai , linux-kernel , devicetree , linux-arm-kernel , linux-clk , "open list:THERMAL" , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 488 Lines: 11 On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote: > The CPUX clock, which is the main clock of the ARM core on Allwinner H3, > can be adjusted by changing the frequency of the PLL_CPUX clock. > > Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX > clock can be adjusted when adjusting the CPUX clock. > > Signed-off-by: Icenowy Zheng Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Reviewed-by: Chen-Yu Tsai