Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752891AbdGXJud (ORCPT ); Mon, 24 Jul 2017 05:50:33 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:34724 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750998AbdGXJuZ (ORCPT ); Mon, 24 Jul 2017 05:50:25 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3B20B606B7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org Subject: Re: [PATCH v1 1/6] phy: qcom-qmp: Fix phy pipe clock gating To: Stephen Boyd , Kishon Vijay Abraham I , Felipe Balbi Cc: linux-arm-msm@vger.kernel.org, Vivek Gautam , Jaehoon Chung , Yoshihiro Shimoda , Fengguang Wu , Wei Yongjun , "open list:GENERIC PHY FRAMEWORK" References: <1500634921-25914-1-git-send-email-mgautam@codeaurora.org> <1500634921-25914-2-git-send-email-mgautam@codeaurora.org> <9085f995-aac0-1033-59e7-8794916fb583@codeaurora.org> From: Manu Gautam Message-ID: Date: Mon, 24 Jul 2017 15:20:18 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <9085f995-aac0-1033-59e7-8794916fb583@codeaurora.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2452 Lines: 48 On 7/21/2017 10:29 PM, Stephen Boyd wrote: > On 07/21/2017 04:01 AM, Manu Gautam wrote: >> From: Vivek Gautam >> >> Pipe clock comes out of the phy and is available as long as >> the phy is turned on. Clock controller fails to gate this >> clock after the phy is turned off and generates a warning. >> >> / # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on' >> [ 33.048585] ------------[ cut here ]------------ >> [ 33.052621] WARNING: CPU: 1 PID: 18 at ../drivers/clk/qcom/clk-branch.c:97 clk_branch_wait+0xf0/0x108 >> [ 33.057384] Modules linked in: >> [ 33.066497] CPU: 1 PID: 18 Comm: kworker/1:0 Tainted: G W 4.12.0-rc7-00024-gfe926e34c36d-dirty #96 >> [ 33.069451] Hardware name: Qualcomm Technologies, Inc. DB820c (DT) >> ... >> [ 33.278565] [] clk_branch_wait+0xf0/0x108 >> [ 33.286375] [] clk_branch2_disable+0x28/0x34 >> [ 33.291761] [] clk_core_disable+0x5c/0x88 >> [ 33.297660] [] clk_core_disable_lock+0x20/0x34 >> [ 33.303129] [] clk_disable+0x1c/0x24 >> [ 33.309384] [] qcom_qmp_phy_poweroff+0x20/0x48 >> [ 33.314328] [] phy_power_off+0x80/0xdc >> [ 33.320492] [] dwc3_core_exit+0x94/0xa0 >> [ 33.325784] [] dwc3_suspend_common+0x50/0x60 >> [ 33.331080] [] dwc3_runtime_suspend+0x48/0x6c >> [ 33.336810] [] pm_generic_runtime_suspend+0x28/0x38 >> [ 33.342627] [] __rpm_callback+0x150/0x254 >> [ 33.349222] [] rpm_callback+0x24/0x78 >> [ 33.354604] [] rpm_suspend+0xe0/0x4e4 >> [ 33.359813] [] pm_runtime_work+0xdc/0xf0 >> [ 33.365028] [] process_one_work+0x12c/0x28c >> [ 33.370576] [] worker_thread+0x58/0x3b8 >> [ 33.376393] [] kthread+0x100/0x12c >> [ 33.381776] [] ret_from_fork+0x10/0x50 >> >> Fix this by enabling pipe clock at the end of phy_init(), and disabling >> it as the first thing in phy_exit(). >> >> Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") >> >> Signed-off-by: Vivek Gautam > Missing your signoff? Also, the fixes tag should be right before signoff > without a newline between. > Will fix it in next version.