Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753778AbdGXKW4 (ORCPT ); Mon, 24 Jul 2017 06:22:56 -0400 Received: from terminus.zytor.com ([65.50.211.136]:33165 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751359AbdGXKWe (ORCPT ); Mon, 24 Jul 2017 06:22:34 -0400 Date: Mon, 24 Jul 2017 03:16:58 -0700 From: tip-bot for Stephane Eranian Message-ID: Cc: kan.liang@intel.com, hpa@zytor.com, peterz@infradead.org, acme@redhat.com, alexander.shishkin@linux.intel.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, vincent.weaver@maine.edu, tglx@linutronix.de, jolsa@redhat.com, eranian@google.com, mingo@kernel.org Reply-To: hpa@zytor.com, alexander.shishkin@linux.intel.com, peterz@infradead.org, acme@redhat.com, kan.liang@intel.com, eranian@google.com, mingo@kernel.org, torvalds@linux-foundation.org, vincent.weaver@maine.edu, linux-kernel@vger.kernel.org, tglx@linutronix.de, jolsa@redhat.com In-Reply-To: <1499967350-10385-2-git-send-email-kan.liang@intel.com> References: <1499967350-10385-2-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/urgent] perf/x86/intel/uncore: Fix Skylake UPI PMU event masks Git-Commit-ID: b3625980a65db6b6b6bbd5790a77ab95ce6397c5 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2730 Lines: 61 Commit-ID: b3625980a65db6b6b6bbd5790a77ab95ce6397c5 Gitweb: http://git.kernel.org/tip/b3625980a65db6b6b6bbd5790a77ab95ce6397c5 Author: Stephane Eranian AuthorDate: Thu, 13 Jul 2017 10:35:45 -0700 Committer: Ingo Molnar CommitDate: Mon, 24 Jul 2017 11:13:17 +0200 perf/x86/intel/uncore: Fix Skylake UPI PMU event masks This patch fixes the event_mask and event_ext_mask for the Intel Skylake Server UPI PMU. Bit 21 is not used as a filter. The extended umask is from bit 32 to bit 55. Correct both umasks. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang Acked-by: Peter Zijlstra Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1499967350-10385-2-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/uncore_snbep.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index dae2fed..19a00a7 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -316,7 +316,7 @@ #define SKX_UPI_PCI_PMON_CTL0 0x350 #define SKX_UPI_PCI_PMON_CTR0 0x318 #define SKX_UPI_PCI_PMON_BOX_CTL 0x378 -#define SKX_PMON_CTL_UMASK_EXT 0xff +#define SKX_UPI_CTL_UMASK_EXT 0xffefff /* SKX M2M */ #define SKX_M2M_PCI_PMON_CTL0 0x228 @@ -328,7 +328,7 @@ DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6"); DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7"); DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); -DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-39"); +DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55"); DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16"); DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); @@ -3603,8 +3603,8 @@ static struct intel_uncore_type skx_uncore_upi = { .perf_ctr_bits = 48, .perf_ctr = SKX_UPI_PCI_PMON_CTR0, .event_ctl = SKX_UPI_PCI_PMON_CTL0, - .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, - .event_mask_ext = SKX_PMON_CTL_UMASK_EXT, + .event_mask = SNBEP_PMON_RAW_EVENT_MASK, + .event_mask_ext = SKX_UPI_CTL_UMASK_EXT, .box_ctl = SKX_UPI_PCI_PMON_BOX_CTL, .ops = &skx_upi_uncore_pci_ops, .format_group = &skx_upi_uncore_format_group,