Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756108AbdGXNij (ORCPT ); Mon, 24 Jul 2017 09:38:39 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:38143 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932101AbdGXNf6 (ORCPT ); Mon, 24 Jul 2017 09:35:58 -0400 From: Ricardo Ribalda Delgado To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Rex Zhu , Tom St Denis , Eric Huang , Huang Rui , Dan Carpenter , "Edward O'Callaghan" , Kees Cook , "Andrew F. Davis" , Hawking Zhang , Baoyou Xie , Masahiro Yamada , Colin Ian King , =?UTF-8?q?Nils=20Wallm=C3=A9nius?= , Joe Perches , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Ricardo Ribalda Delgado Subject: [PATCH 07/14] amdgpu: powerplay: polaris10_smc: Assume display_config is zero Date: Mon, 24 Jul 2017 15:35:33 +0200 Message-Id: <20170724133540.32200-8-ricardo.ribalda@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170724133540.32200-1-ricardo.ribalda@gmail.com> References: <20170724133540.32200-1-ricardo.ribalda@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1353 Lines: 30 display_config is never set, we can assume it is zero. Signed-off-by: Ricardo Ribalda Delgado --- drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c index f68e759e8be2..c889fc930cfc 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c @@ -711,11 +711,12 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, level->DownHyst = 0; level->VoltageDownHyst = 0; level->PowerThrottle = 0; - data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr; + data->display_timing.min_clock_in_sr = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) - level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock, - hwmgr->display_config.min_core_set_clock_in_sr); + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep)) + level->DeepSleepDivId = + smu7_get_sleep_divider_id_from_clock(clock, 0); /* Default to slow, highest DPM level will be * set to PPSMC_DISPLAY_WATERMARK_LOW later. -- 2.13.2