Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756143AbdGXNjW (ORCPT ); Mon, 24 Jul 2017 09:39:22 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:35230 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932079AbdGXNfx (ORCPT ); Mon, 24 Jul 2017 09:35:53 -0400 From: Ricardo Ribalda Delgado To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Rex Zhu , Tom St Denis , Eric Huang , Huang Rui , Dan Carpenter , "Edward O'Callaghan" , Kees Cook , "Andrew F. Davis" , Hawking Zhang , Baoyou Xie , Masahiro Yamada , Colin Ian King , =?UTF-8?q?Nils=20Wallm=C3=A9nius?= , Joe Perches , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Ricardo Ribalda Delgado Subject: [PATCH 04/14] amdgpu: powerplay: smu7_hwmgr: Assume display_config is zero Date: Mon, 24 Jul 2017 15:35:30 +0200 Message-Id: <20170724133540.32200-5-ricardo.ribalda@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170724133540.32200-1-ricardo.ribalda@gmail.com> References: <20170724133540.32200-1-ricardo.ribalda@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2193 Lines: 51 display_config is never set, so we can assume it is zero. Signed-off-by: Ricardo Ribalda Delgado --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 1f01020ce3a9..893e6e846284 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -2727,9 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, cgs_get_active_displays_info(hwmgr->device, &info); - minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; - minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); @@ -3928,7 +3925,7 @@ smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) num_active_displays = info.display_count; - if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true) + if (num_active_displays > 1) smu7_notify_smc_display_change(hwmgr, false); return 0; @@ -4032,12 +4029,12 @@ smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) if (data->display_timing.num_existing_displays != info.display_count) is_update_required = true; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr && - (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || - hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) - is_update_required = true; - } + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep) && + data->display_timing.min_clock_in_sr && + data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK) + is_update_required = true; + return is_update_required; } -- 2.13.2