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From: Mathieu Poirier <mathieu.poirier@linaro.org>
Date: Mon, 24 Jul 2017 11:12:48 -0600
Message-ID: <CANLsYkzMSTXaCk5d_J8Ea4wpoqbfnDx0jCrwodxkSc7hrzLEgQ@mail.gmail.com>
Subject: Re: [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Mike Leach <mike.leach@linaro.org>
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On 20 July 2017 at 04:17, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
> The coresight SoC 600 supports ETR save-restore which allows us
> to restore a trace session by retaining the RRP/RWP/STS.Full values
> when the TMC leaves the Disabled state. However, the TMC doesn't
> have a scatter-gather unit in built.
>
> Also, TMCs have different PIDs in different configurations (ETF,
> ETB & ETR), unlike the previous generation.
>
> While the DEVID exposes some of the features/changes in the TMC,
> it doesn't explicitly advertises the new save-restore feature
> as described above.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 16 ++++++++++++++++
>  drivers/hwtracing/coresight/coresight-tmc.h |  4 ++++
>  2 files changed, 20 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index c4a5dea..e754a3e 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -442,6 +442,22 @@ static struct amba_id tmc_ids[] = {
>                 .id     = 0x000bb961,
>                 .mask   = 0x000fffff,
>         },
> +       {
> +               /* Coresight SoC 600 TMC-ETR/ETS */
> +               .id     = 0x000bb9e8,
> +               .mask   = 0x000fffff,
> +               .data   = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,

It the casting to unsigned long mandatory?

> +       },
> +       {
> +               /* Coresight SoC 600 TMC-ETB */
> +               .id     = 0x000bb9e9,
> +               .mask   = 0x000fffff,
> +       },
> +       {
> +               /* Coresight SoC 600 TMC-ETF */
> +               .id     = 0x000bb9ea,
> +               .mask   = 0x000fffff,
> +       },
>         { 0, 0},
>  };
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 08f1aea..f24e89a 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -130,6 +130,10 @@ enum tmc_mem_intf_width {
>   */
>  #define TMC_ETR_SAVE_RESTORE           (0x1U << 2)
>
> +/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
> +#define CORESIGHT_SOC_600_ETR_CAPS     \
> +       (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
> +
>  /**
>   * struct tmc_drvdata - specifics associated to an TMC component
>   * @base:      memory mapped base address for this component.
> --
> 2.7.5
>