Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756766AbdGXTNL (ORCPT ); Mon, 24 Jul 2017 15:13:11 -0400 Received: from mail-it0-f65.google.com ([209.85.214.65]:38349 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755969AbdGXTJv (ORCPT ); Mon, 24 Jul 2017 15:09:51 -0400 Date: Mon, 24 Jul 2017 14:09:49 -0500 From: Rob Herring To: fenglinw@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, Linus Walleij , Mark Rutland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, collinsd@codeaurora.org, aghayal@codeaurora.org, wruan@codeaurora.org, kgunda@codeaurora.org Subject: Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Add support for qcom,gpios-disallowed property Message-ID: <20170724190949.y45cx4zextmvb4tn@rob-hp-laptop> References: <20170719071804.3816-1-fenglinw@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170719071804.3816-1-fenglinw@codeaurora.org> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1616 Lines: 35 On Wed, Jul 19, 2017 at 03:17:07PM +0800, fenglinw@codeaurora.org wrote: > From: Fenglin Wu > > Add support for qcom,gpios-disallowed property which is used to exclude > PMIC GPIOs not owned by the APSS processor from the pinctrl device. > > Signed-off-by: Fenglin Wu > --- > .../devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 12 ++ > drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 202 +++++++++++++++++---- > 2 files changed, 176 insertions(+), 38 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > index 8d893a8..435efe8 100644 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > @@ -43,6 +43,17 @@ PMIC's from Qualcomm. > the first cell will be used to define gpio number and the > second denotes the flags for this gpio > > +- qcom,gpios-disallowed: > + Usage: optional > + Value type: > + Definition: Array of the GPIO hardware numbers corresponding to GPIOs > + which the APSS processor is not allowed to configure. > + The hardware numbers are indexed from 1. > + The interrupt resources for these GPIOs must not be defined > + in "interrupts" and "interrupt-names" properties. > + GPIOs defined in this array won't be registered as pins > + in the pinctrl device or gpios in the gpio chip. Isn't simply not assigning GPIOs to anything in the DT sufficient to not use GPIOs? Rob