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1;BY2PR12MB0145;20:RkKlNZZiVkhxMeJqCTi9fxemrBobBQ4PdxJIE9LBlbGCaDBMXal5OkXH/B1ZWf7IL6PByW2ox+iPeXT3ELe4UQxKeXtuCNbeg1MGJ8UZPQHp7RIs7V+fbDtU1nR6xhD8RwX6z87YS4UCp/vmhwRknKBUBdmp02e5vI92cnifpM7NbQLj9Hc/RC7BywCIIVS75ylS3acZ9ZBwpTruYA8wM1hITZE+AzUGcH+6yX3M7FIaPk6H7fwTHlbsOnfeo+Dl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2017 20:03:51.8222 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR12MB0145 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 998 Lines: 29 On #UD, x86_emulate_instruction() fetches the data from guest memory and decodes the instruction bytes to assist further. When SEV is enabled, the instruction bytes will be encrypted using the guest-specific key, hypervisor will no longer able to fetch the instruction bytes to assist UD handling. By not installing intercept we let the guest receive and handle #UD. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 64b9f60..4581d03 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1432,8 +1432,10 @@ static void init_vmcb(struct vcpu_svm *svm) svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; } - if (sev_guest(svm->vcpu.kvm)) + if (sev_guest(svm->vcpu.kvm)) { svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE; + clr_exception_intercept(svm, UD_VECTOR); + } mark_all_dirty(svm->vmcb); -- 2.9.4