Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751803AbdGYKhT (ORCPT ); Tue, 25 Jul 2017 06:37:19 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5899 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751466AbdGYKeg (ORCPT ); Tue, 25 Jul 2017 06:34:36 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 25 Jul 2017 03:34:36 -0700 From: Peter De Schrijver To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Thierry Reding , Jonathan Hunter , , , Subject: [PATCH 09/14] clk: tegra: don't warn for pll_d2 defaults unnecessarily Date: Tue, 25 Jul 2017 13:34:10 +0300 Message-ID: <1500978856-5981-10-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com> References: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1176 Lines: 35 If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver Reviewed-by: Timo Alho --- drivers/clk/tegra/clk-tegra210.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index a4d7d94..1e470ca 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -718,8 +718,6 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, plldss->params->defaults_set = true; if (val & PLL_ENABLE) { - pr_warn("%s already enabled. Postponing set full defaults\n", - pll_name); /* * PLL is ON: check if defaults already set, then set those @@ -758,6 +756,10 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, (~PLLDSS_MISC1_CFG_EN_SDM)); } + if (!plldss->params->defaults_set) + pr_warn("%s already enabled. Postponing set full defaults\n", + pll_name); + /* Enable lock detect */ if (val & PLLDSS_BASE_LOCK_OVERRIDE) { val &= ~PLLDSS_BASE_LOCK_OVERRIDE; -- 1.9.1