Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751965AbdGZAgX (ORCPT ); Tue, 25 Jul 2017 20:36:23 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41866 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751402AbdGZAgU (ORCPT ); Tue, 25 Jul 2017 20:36:20 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2873E604FD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Tue, 25 Jul 2017 17:36:18 -0700 From: Stephen Boyd To: Icenowy Zheng Cc: Liam Girdwood , Mark Brown , Maxime Ripard , Chen-Yu Tsai , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 Message-ID: <20170726003618.GG2146@codeaurora.org> References: <20170723102749.17323-1-icenowy@aosc.io> <20170723102749.17323-7-icenowy@aosc.io> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170723102749.17323-7-icenowy@aosc.io> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 519 Lines: 15 On 07/23, Icenowy Zheng wrote: > The CPUX clock, which is the main clock of the ARM core on Allwinner H3, > can be adjusted by changing the frequency of the PLL_CPUX clock. > > Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX > clock can be adjusted when adjusting the CPUX clock. > > Signed-off-by: Icenowy Zheng > --- Acked-by: Stephen Boyd -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project