Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751638AbdGZDwL (ORCPT ); Tue, 25 Jul 2017 23:52:11 -0400 Received: from mx2.suse.de ([195.135.220.15]:41500 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751228AbdGZDwK (ORCPT ); Tue, 25 Jul 2017 23:52:10 -0400 Date: Wed, 26 Jul 2017 05:51:23 +0200 From: Borislav Petkov To: Suravee Suthikulpanit Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com Subject: Re: [PATCH] x86/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask Message-ID: <20170726035123.GA30702@nazgul.tnic> References: <1500544328-2132-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1500544328-2132-1-git-send-email-suravee.suthikulpanit@amd.com> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2223 Lines: 63 On Thu, Jul 20, 2017 at 04:52:08AM -0500, Suravee Suthikulpanit wrote: > With X86_FEATURE_TOPOEXT, current logic default to using APIC ID > to calculate cpumask for shared_cpu_map. However, since APIC IDs > are not guarantee to be contiguous for cores across different L3, > such as in family17h system w/ downcore configuration. > This results in incorrect L3 shared_cpu_map. There are syntactic and formulation errors in this paragraph, it reads funny. Please improve. > Instead, it should be safe to always use the pre-calculated > cpu_llc_shared_mask to derive L3 shared_cpu_map. "should"?!? What does that mean? You tested it on relevant machines or you're hoping that nothing would go wrong? > Signed-off-by: Suravee Suthikulpanit > --- > arch/x86/kernel/cpu/intel_cacheinfo.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c > index c55fb2c..10427bb 100644 > --- a/arch/x86/kernel/cpu/intel_cacheinfo.c > +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c > @@ -811,7 +811,20 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int index, > struct cacheinfo *this_leaf; > int i, sibling; > > - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { > + if (index == 3) { > + for_each_cpu(i, cpu_llc_shared_mask(cpu)) { > + this_cpu_ci = get_cpu_cacheinfo(i); > + if (!this_cpu_ci->info_list) > + continue; > + this_leaf = this_cpu_ci->info_list + index; > + for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) { > + if (!cpu_online(sibling)) > + continue; > + cpumask_set_cpu(sibling, > + &this_leaf->shared_cpu_map); > + } > + } > + } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { So this leaves more questions open than before it: * Is cpu_llc_shared_map now *the* mask for the L3? * Is the X86_FEATURE_TOPOEXT thing still going to be used for the other cache levels? Apparently yes, I guess. IOW, what is the big picture here? I could use some more details in the commit message about it. -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --