Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751022AbdGZHlR (ORCPT ); Wed, 26 Jul 2017 03:41:17 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:18693 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750813AbdGZHlQ (ORCPT ); Wed, 26 Jul 2017 03:41:16 -0400 From: Matt Redfearn To: Ralf Baechle CC: , Matt Redfearn , "Maciej W. Rozycki" , , James Hogan , Paul Burton Subject: [PATCH v3 1/2] MIPS: Introduce cpu_tcache_line_size Date: Wed, 26 Jul 2017 08:41:08 +0100 Message-ID: <1501054869-15068-1-git-send-email-matt.redfearn@imgtec.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 942 Lines: 33 There exist macros to return the cache line size of the L1 dcache and L2 scache but there is currently no macro for the L3 tcache. Add this macro which will be used by the following patch "MIPS: PCI: Fix smp_processor_id() in preemptible" Signed-off-by: Matt Redfearn --- Changes in v3: Split into 2 patches Changes in v2: None arch/mips/include/asm/cpu-features.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 8baa9033b181..721b698bfe3c 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -428,6 +428,9 @@ #ifndef cpu_scache_line_size #define cpu_scache_line_size() cpu_data[0].scache.linesz #endif +#ifndef cpu_tcache_line_size +#define cpu_tcache_line_size() cpu_data[0].tcache.linesz +#endif #ifndef cpu_hwrena_impl_bits #define cpu_hwrena_impl_bits 0 -- 2.7.4