Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751592AbdGZKTL (ORCPT ); Wed, 26 Jul 2017 06:19:11 -0400 Received: from foss.arm.com ([217.140.101.70]:58734 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751543AbdGZKTK (ORCPT ); Wed, 26 Jul 2017 06:19:10 -0400 Subject: Re: [PATCH 1/3] ARM: dts: NSP: Add dma-coherent to relevant DT entries To: Jon Mason , Florian Fainelli , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1501020372-19607-1-git-send-email-jon.mason@broadcom.com> <1501020372-19607-2-git-send-email-jon.mason@broadcom.com> From: Robin Murphy Message-ID: <6b419bfc-56e8-5a6d-e995-78fbeca02282@arm.com> Date: Wed, 26 Jul 2017 11:19:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501020372-19607-2-git-send-email-jon.mason@broadcom.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4453 Lines: 151 Hi Jon, On 25/07/17 23:06, Jon Mason wrote: > Cache related issues with DMA rings and performance issues related to > caching are being caused by not properly setting the "dma-coherent" flag > in the device tree entries. Adding it here to correct the issue. > > Signed-off-by: Jon Mason > Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support") > Fixes: 3107fa5bcfb2 ("ARM: dts: NSP: Add SD/MMC support") > Fixes: 13d04f20935c ("ARM: dts: NSP: Add AMAC entries") > Fixes: 5aeda7bf8a1e ("ARM: dts: NSP: Add and enable amac2") > Fixes: 17d517172300 ("ARM: dts: NSP: Add mailbox (PDC) to NSP") > Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree") > Fixes: bf2289bedef4 ("ARM: dts: NSP: Add Switch Register Access Block node") > Fixes: 0f9f27a36d09 ("ARM: dts: NSP: Add I2C support to the DT") > Fixes: 8dbcad020f2e ("ARM: dts: nsp: Add sata device tree entry") > Fixes: 522199029fdc ("ARM: dts: NSP: Fix PCIE DT issue") > --- > arch/arm/boot/dts/bcm-nsp.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi > index 7204d1def23d..c8d734d9f5fc 100644 > --- a/arch/arm/boot/dts/bcm-nsp.dtsi > +++ b/arch/arm/boot/dts/bcm-nsp.dtsi > @@ -207,6 +207,7 @@ > clocks = <&iprocslow>; > clock-names = "apb_pclk"; > #dma-cells = <1>; > + dma-coherent; Just to check, does this actually work? I ask because the pl330 driver currently never sets src_cache_ctrl/dst_cache_ctrl to anything other than noncacheable nonbufferable, so if your interconnect respects those attributes this seems liable to make things go wrong under current kernels, even if it is an accurate description of the hardware. If on the other hand the interconnect does its own magic and will manage to snoop caches appropriately regardless of AXI attributes, then I guess it's fine, if a little scary ;) Robin. > }; > > sdio: sdhci@21000 { > @@ -215,6 +216,7 @@ > interrupts = ; > sdhci,auto-cmd12; > clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; > + dma-coherent; > status = "disabled"; > }; > > @@ -224,6 +226,7 @@ > <0x110000 0x1000>; > reg-names = "amac_base", "idm_base"; > interrupts = ; > + dma-coherent; > status = "disabled"; > }; > > @@ -233,6 +236,7 @@ > <0x111000 0x1000>; > reg-names = "amac_base", "idm_base"; > interrupts = ; > + dma-coherent; > status = "disabled"; > }; > > @@ -242,6 +246,7 @@ > <0x112000 0x1000>; > reg-names = "amac_base", "idm_base"; > interrupts = ; > + dma-coherent; > status = "disabled"; > }; > > @@ -252,6 +257,7 @@ > #mbox-cells = <1>; > brcm,rx-status-len = <32>; > brcm,use-bcm-hdr; > + dma-coherent; > }; > > nand: nand@26000 { > @@ -325,6 +331,7 @@ > compatible = "generic-ehci"; > reg = <0x2a000 0x100>; > interrupts = ; > + dma-coherent; > status = "disabled"; > }; > > @@ -332,6 +339,7 @@ > compatible = "generic-ohci"; > reg = <0x2b000 0x100>; > interrupts = ; > + dma-coherent; > status = "disabled"; > }; > > @@ -364,6 +372,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > + dma-coherent; > status = "disabled"; > > /* ports are defined in board DTS */ > @@ -376,6 +385,7 @@ > #size-cells = <0>; > interrupts = ; > clock-frequency = <100000>; > + dma-coherent; > status = "disabled"; > }; > > @@ -446,6 +456,7 @@ > interrupts = ; > #address-cells = <1>; > #size-cells = <0>; > + dma-coherent; > status = "disabled"; > > sata0: sata-port@0 { > @@ -483,6 +494,7 @@ > */ > ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; > > + dma-coherent; > status = "disabled"; > > msi-parent = <&msi0>; > @@ -519,6 +531,7 @@ > */ > ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; > > + dma-coherent; > status = "disabled"; > > msi-parent = <&msi1>; > @@ -555,6 +568,7 @@ > */ > ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; > > + dma-coherent; > status = "disabled"; > > msi-parent = <&msi2>; >