Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751606AbdGZKbk (ORCPT ); Wed, 26 Jul 2017 06:31:40 -0400 Received: from anglina.eu ([195.181.215.36]:59876 "EHLO megous.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751421AbdGZKbi (ORCPT ); Wed, 26 Jul 2017 06:31:38 -0400 X-Greylist: delayed 460 seconds by postgrey-1.27 at vger.kernel.org; Wed, 26 Jul 2017 06:31:37 EDT Message-ID: <1501064628.14577.1.camel@megous.com> Subject: Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC From: =?UTF-8?Q?Ond=C5=99ej?= Jirman To: icenowy@aosc.io, wens@csie.org Cc: Liam Girdwood , Mark Brown , Maxime Ripard , linux-kernel , devicetree , linux-arm-kernel , linux-clk , "open list:THERMAL" , linux-sunxi Date: Wed, 26 Jul 2017 12:23:48 +0200 In-Reply-To: <82507f40a1ddba8517cf09f51d3afa33@aosc.io> References: <20170723102749.17323-1-icenowy@aosc.io> <20170723102749.17323-11-icenowy@aosc.io> <25C8A89C-8495-4787-934C-8E9667CD70BF@aosc.io> <82507f40a1ddba8517cf09f51d3afa33@aosc.io> Content-Type: multipart/signed; micalg="pgp-sha256"; protocol="application/pgp-signature"; boundary="=-pnR/cDIPKuRWxVR3bWQJ" Mime-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2610 Lines: 78 --=-pnR/cDIPKuRWxVR3bWQJ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, icenowy@aosc.io p=C3=AD=C5=A1e v St 26. 07. 2017 v 15:36 +0800: >=20 > > > >=20 > > > > Otherwse > > > >=20 > > > > > + regulator-max-microvolt =3D <1400000>; > > > > > + regulator-ramp-delay =3D <200>; > > > >=20 > > > > Is this an actual constraint of the SoC? Or is it a characteristic > > > > of the regulator? If it is the latter, it belongs in the driver. > > > > AFAIK the regulator supports varying the ramp delay (slew rate). >=20 > I don't know... >=20 > Maybe I should ask Ondrej? It is probably neither. It is used to calculate a delay inserted by the kernel between setting a new target voltage over I2C and changing the frequency of the CPU. The actual delay is calculated by the difference between previous and the new voltage. I don't remember seeing anything in the datasheet of the regulator. This is just some low value that works. It would probably be dependent on the capacitance on the output of the regulator, actual load (which varies), etc. So it is a board specific value. One could measure it with an oscilloscope if there's a need to optimize this. regards, o. > > > >=20 > > > > ChenYu > > > >=20 > > > > > + regulator-boot-on; > > > > > + regulator-always-on; > > > > > + }; > > > > > +}; > > > > > + > > > > > &r_pio { > > > > > leds_r_opc: led_pins@0 { > > > > > pins =3D "PL10"; > > > > > -- > > > > > 2.13.0 > > > > >=20 --=-pnR/cDIPKuRWxVR3bWQJ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEmrE4sgaRYhzUz5ICbmQmxnfP7/EFAll4bbQACgkQbmQmxnfP 7/EnUxAAjMqGccKdIgDwrz7xLA5Y0mZNYu5UEncp+4oEt/QplG2q0/+G4d1Bxgwl 3iNhQ/l+KF6KWtT6JIhgU7i11UZL0a0Qz9sxI0JxAxy/U+i3tTMlPm5KOaipWTgX HIA4lzv6VWscG0XH9DU5qCX3Re+eqgCzJfBNMYZ216e27/jLYf5AP7Kyo8sIC73X VdVMw9xuQgXvDpiCuHJpXUqv6/5p09Hm6YRC7H4+vJhf8w+T8XLwIYb9TfeMo9E4 OZkcuWLYkza9osSj4sBlCTFjno1dsVbqE8fAj1FM9naWs3mKzUMUNMfo21b2LRj3 zOd7nkgK0AE70EilSrvfRgYvjRnw/X1b9Tk6d3afXxF3VYtTF6w7MFtHqxhH4EDR 1j+ABNPcquJqtBzjgH718btgQKlj6Gxkh/TwYnlp3asGQtdpG6QU2E5Fzd5PLgNh a/GmkulExnL4DTe8QG1fcz1xqKMF0QVKv8P0VdFY3UjX2/7SIB4YhFLLMLo77QwP ibMIOIIajB6HtnorXV/o6rtFd09ILeLxSKfz+f9I3fZbJbetn8trKH3+IZQd1Fu4 OVIxASQhBhZduX6IsF73aYlJqnQknPz/LrCe9kx0lG875nfky44PSTLqGUkU/RL3 mcVL1XBv/8Ab/YRlgq8pr7emE05MIBkpzsB6OaeGEeEdF9/jvr0= =7I9k -----END PGP SIGNATURE----- --=-pnR/cDIPKuRWxVR3bWQJ--