Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751613AbdG0LK5 (ORCPT ); Thu, 27 Jul 2017 07:10:57 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58238 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751530AbdG0LKs (ORCPT ); Thu, 27 Jul 2017 07:10:48 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8555560998 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [RFC 02/12] clk: qcom: flag for 64 bit CONFIG_CTL Date: Thu, 27 Jul 2017 16:40:15 +0530 Message-Id: <1501153825-5181-3-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501153825-5181-1-git-send-email-absahu@codeaurora.org> References: <1501153825-5181-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1881 Lines: 47 Some of the Alpha PLL’s (like Spark, Brammo PLL) do not have CONFIG_CTL_U register. This patch adds the flag for PLL’s which have CONFIG_CTL_U register and checks the same while doing PLL initial configuration. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 5 ++++- drivers/clk/qcom/clk-alpha-pll.h | 7 ++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 47a1da3..e6cde2d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -118,7 +118,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_write(regmap, off + PLL_L_VAL, config->l); regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha); regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val); - regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val); + + if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL) + regmap_write(regmap, off + PLL_CONFIG_CTL_U, + config->config_ctl_hi_val); val = config->main_output_mask; val |= config->aux_output_mask; diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d6e1ee2..bbd6aa9 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -34,9 +34,10 @@ struct clk_alpha_pll { const struct pll_vco *vco_table; size_t num_vco; -#define SUPPORTS_OFFLINE_REQ BIT(0) -#define SUPPORTS_16BIT_ALPHA BIT(1) -#define SUPPORTS_FSM_MODE BIT(2) +#define SUPPORTS_OFFLINE_REQ BIT(0) +#define SUPPORTS_16BIT_ALPHA BIT(1) +#define SUPPORTS_FSM_MODE BIT(2) +#define SUPPORTS_64BIT_CONFIG_CTL BIT(3) u8 flags; struct clk_regmap clkr; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation