Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751813AbdG1JUR (ORCPT ); Fri, 28 Jul 2017 05:20:17 -0400 Received: from mail-lf0-f53.google.com ([209.85.215.53]:35603 "EHLO mail-lf0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751768AbdG1JUP (ORCPT ); Fri, 28 Jul 2017 05:20:15 -0400 Subject: Re: [PATCH 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller To: Ryder Lee , Hans de Goede , Tejun Heo Cc: Rob Herring , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, Long Cheng References: <45c7b2abc65b0d7b5b945763837811296e56835f.1501134896.git.ryder.lee@mediatek.com> From: Sergei Shtylyov Message-ID: <7adf5e2c-4678-3e91-1036-f5e82d23329f@cogentembedded.com> Date: Fri, 28 Jul 2017 12:20:04 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <45c7b2abc65b0d7b5b945763837811296e56835f.1501134896.git.ryder.lee@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2910 Lines: 78 Hello! On 7/27/2017 9:38 AM, Ryder Lee wrote: > Add DT bindings for the onboard SATA controller present on the MediaTek > SoCs. > > Signed-off-by: Ryder Lee > --- > Documentation/devicetree/bindings/ata/ahci-mtk.txt | 48 ++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt > > diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt > new file mode 100644 > index 0000000..a8d11db > --- /dev/null > +++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt > @@ -0,0 +1,48 @@ > +MediaTek Seria ATA controller > + > +Required properties: > + - compatible : Must be "mediatek,ahci". > + - reg : Physical base addresses and length of register sets. > + - interrupts : Interrupt associated with the SATA device. > + - interrupt-names : Associated name must be: "hostc". > + - clocks : The phandle for the clock. Your example shows that you need both phandle and specifier (afetr phandle). > + - clock-names : Associated name must be: "ahb", "axi", "asic", "rbc", "pm" > + - phys : The phandle for the PHY port. Likewise. > + - phy-names : Associated name must be: "sata-phy". > + - ports-implemented : Mask that indicates which ports that the HBA supports > + are available for software to use. Useful if PORTS_IMPL > + is not programmed by the BIOS, which is true with some > + embedded SOC's. An empty line wouldn't hurt here... > +Optional properties: > + - power-domains : A phandle and power domain specifier pair to the power > + domain which is responsible for collapsing and restoring > + power to the peripheral. > + - resets : Must contain an entry for each entry in reset-names. > + See ../reset/reset.txt for details. > + - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst". > + - mediatek,phy-mode : A phandle to the system controller, used to enable > + SATA function. > + > +Example: > + > + sata: sata@1a200000 { > + compatible = "mediatek,ahci"; > + reg = <0 0x1a200000 0 0x1100>; > + interrupts = ; > + interrupt-names = "hostc"; > + clocks = <&pciesys CLK_SATA_AHB_EN>, > + <&pciesys CLK_SATA_AXI_EN>, > + <&pciesys CLK_SATA_ASIC_EN>, > + <&pciesys CLK_SATA_RBC_EN>, > + <&pciesys CLK_SATA_PM_EN>; > + clock-names = "ahb", "axi", "asic", "rbc", "pm"; > + phys = <&u3port1 PHY_TYPE_SATA>; > + phy-names = "sata-phy"; > + ports-implemented = <0x1>; > + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, > + <&pciesys MT7622_SATA_PHY_SW_RST>, > + <&pciesys MT7622_SATA_PHY_REG_RST>; > + reset-names = "axi-rst", "sw-rst", "reg-rst"; > + mediatek,phy-mode = <&pciesys>; > + }; MBR, Sergei