Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753285AbdG2AGF (ORCPT ); Fri, 28 Jul 2017 20:06:05 -0400 Received: from mail-qk0-f172.google.com ([209.85.220.172]:34280 "EHLO mail-qk0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752991AbdG2AGD (ORCPT ); Fri, 28 Jul 2017 20:06:03 -0400 MIME-Version: 1.0 In-Reply-To: References: <20170728204558.6455-1-brendanhiggins@google.com> <20170728204558.6455-2-brendanhiggins@google.com> From: Brendan Higgins Date: Fri, 28 Jul 2017 17:06:02 -0700 Message-ID: Subject: Re: [PATCH v2 1/1] i2c: aspeed: add proper support fo 24xx clock params To: Rick Altherr Cc: Wolfram Sang , Benjamin Herrenschmidt , Joel Stanley , Robi Buranyi , OpenBMC Maillist , linux-i2c@vger.kernel.org, Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 714 Lines: 14 On Fri, Jul 28, 2017 at 2:00 PM, Rick Altherr wrote: > Is clk_fractional_divider from include/linux/clk-provider.h appropriate here? > Alas, no. clk_fractional_divider is not flexible enough to specify the divider the way that it is represented in the Aspeed 24xx/25xx parts which have the divider expressed as a "base clock" which is always a power of 2 along with the time where SCL is high and the time that the SCL is low in units of base clock. Thus, there are two separate "numerator" values and the denominator is represented as the ilog2 of the actual value. That being said, I could implement this as a custom clock subclass, which would probably be cleaner that what I have done.