Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751599AbdGaGdT (ORCPT ); Mon, 31 Jul 2017 02:33:19 -0400 Received: from smtprelay2.synopsys.com ([198.182.60.111]:50580 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751075AbdGaGdR (ORCPT ); Mon, 31 Jul 2017 02:33:17 -0400 Subject: Re: [PATCH 5/5] ARC: DTS: Add device-tree for Anarion-based development board To: Alexandru Gagniuc , "linux-snps-arc@lists.infradead.org" , "linux-kernel@vger.kernel.org" CC: Rob Herring , Mark Rutland , "devicetree@vger.kernel.org" References: <20170728220707.13960-1-alex.g@adaptrum.com> <20170728220707.13960-6-alex.g@adaptrum.com> From: Vineet Gupta Message-ID: <8576ceb3-036f-6357-fb52-b062dfe5fa57@synopsys.com> Date: Mon, 31 Jul 2017 12:02:58 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170728220707.13960-6-alex.g@adaptrum.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.12.196.15] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4974 Lines: 190 On 07/29/2017 03:37 AM, Alexandru Gagniuc wrote: > Signed-off-by: Alexandru Gagniuc > --- > arch/arc/boot/dts/adaptrum_anarion.dtsi | 107 ++++++++++++++++++++++++++++ > arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +++++++++++++ > 2 files changed, 156 insertions(+) > create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi > create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts So you really need to upstream the fpga dts - if this just for initial bringup and you will eventually switch to silicon. The reason I say is every additional file is a maintenance burden so better to avoid things which are only temporary. But if you plan to support this config in long run I'm fine ! Looking further it seems first one is a "common" include style dts while fpga is for actual platform and the SoC one will follow once you get it running ? > > diff --git a/arch/arc/boot/dts/adaptrum_anarion.dtsi b/arch/arc/boot/dts/adaptrum_anarion.dtsi > new file mode 100644 > index 0000000..f50958f > --- /dev/null > +++ b/arch/arc/boot/dts/adaptrum_anarion.dtsi > @@ -0,0 +1,107 @@ > +/* > + * (C) Copyright 2017 Adaptrum, Inc. > + * Written by Alexandru Gagniuc for Adaptrum, Inc. > + * Licensed under the GPLv2 or (at your option) any later version > + */ > + > +#include "skeleton.dtsi" Perhaps put a one liner that this is based on SNPS ARC700 cpu ! > + > +/ { > + compatible = "adaptrum,anarion"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + soc { > + compatible = "simple-bus"; > + device_type = "soc"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + interrupt-parent = <&core_intc>; > + > + core_intc: interrupt-controller { > + compatible = "snps,arc700-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + uart0: serial@f2202100 { > + compatible = "ns16550"; > + reg = <0xf2202100 0x20>; > + interrupts = <8>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <192000000>; > + status = "disabled"; > + }; > + > + uart1: serial@f2202200 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xf2202200 0x20>; > + interrupts = <8>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <192000000>; > + status = "disabled"; > + }; > + > + uart2: serial@f2202300 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xf2202300 0x20>; > + interrupts = <8>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <192000000>; > + status = "disabled"; > + }; > + > + uart3: serial@f2202400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xf2202400 0x20>; > + interrupts = <8>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <192000000>; > + status = "disabled"; > + }; > + > + qspi: qspi@f200f000 { > + compatible = "adaptrum,anarion-qspi"; > + reg = <0xf200f000 0x1000>, > + <0x20000000 0x08000000>; > + > + interrupts = <10>; > + status = "disabled"; > + }; > + > + gmac0: ethernet@f2010000 { > + compatible = "snps,dwmac"; > + reg = <0xf2010000 0x4000>; > + > + interrupt-parent = <&core_intc>; > + interrupts = <20>; > + interrupt-names = "macirq"; > + > + clocks = <&core_clk>; > + clock-names = "stmmaceth"; > + > + snps,pbl = <32>; > + status = "disabled"; > + }; > + > + gmac1: ethernet@f2014000 { > + compatible = "adaptrum,anarion-gmac", "snps,dwmac"; > + reg = <0xf2014000 0x4000>, <0xf2018100 8>; > + > + interrupt-parent = <&core_intc>; > + interrupts = <21>; > + interrupt-names = "macirq"; > + > + clocks = <&core_clk>; > + clock-names = "stmmaceth"; > + > + snps,pbl = <32>; > + status = "disabled"; > + }; > + }; > +}; > diff --git a/arch/arc/boot/dts/adaptrum_anarion_fpga.dts b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts > new file mode 100644 > index 0000000..36173b2 > --- /dev/null > +++ b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts > @@ -0,0 +1,49 @@ > +/* > + * (C) Copyright 2017 Adaptrum, Inc. > + * Written by Alexandru Gagniuc for Adaptrum, Inc. > + * Licensed under the GPLv2 or (at your option) any later version > + */ > + > +/dts-v1/; > + > +#include "adaptrum_anarion.dtsi" > + > +/ { > + model = "adaptrum,anarion"; > + compatible = "adaptrum,anarion"; > + > + chosen { > + bootargs = "earlycon console=ttyS0,115200n8"; > + stdout-path = "serial0:115200n8"; > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + core_clk: core_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <12000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&qspi { > + status = "okay"; > + flash0: w25q128fvn@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "winbond,w25q128", "jedec,spi-nor"; > + spi-max-frequency = <70000000>; > + m25p,fast-read; > + }; > +}; > + > +&gmac1 { > + phy-mode = "rgmii"; > + status = "okay"; > +};