Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752082AbdGaKR6 (ORCPT ); Mon, 31 Jul 2017 06:17:58 -0400 Received: from regular1.263xmail.com ([211.150.99.138]:48261 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750977AbdGaKR4 (ORCPT ); Mon, 31 Jul 2017 06:17:56 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: andy.yan@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: andy.yan@rock-chips.com X-UNIQUE-TAG: <9ae40d56e32e69d915ccdb05c4f91e41> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Andy Yan To: heiko@sntech.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Andy Yan Subject: [PATCH 09/14] ARM: dts: rockchip: add pwm dt node for rv1108 Date: Mon, 31 Jul 2017 18:17:45 +0800 Message-Id: <1501496265-21910-1-git-send-email-andy.yan@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501495449-21290-1-git-send-email-andy.yan@rock-chips.com> References: <1501495449-21290-1-git-send-email-andy.yan@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4397 Lines: 179 Add pwm device tree node for rv1108 Signed-off-by: Andy Yan --- arch/arm/boot/dts/rv1108.dtsi | 143 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 6ae83a8..7fcc6de 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -213,6 +213,54 @@ status = "disabled"; }; + pwm4: pwm@10280000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280000 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@10280010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280010 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@10280020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280020 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm6_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@10280030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280030 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + grf: syscon@10300000 { compatible = "rockchip,rv1108-grf", "syscon"; reg = <0x10300000 0x1000>; @@ -232,6 +280,53 @@ status = "disabled"; }; + pwm0: pwm@20040000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040000 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@20040010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040010 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@20040020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040020 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@20040030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040030 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; pmugrf: syscon@20060000 { compatible = "rockchip,rv1108-pmugrf", "syscon"; reg = <0x20060000 0x1000>; @@ -453,6 +548,54 @@ }; }; + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm4 { + pwm4_pin: pwm4-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm5 { + pwm5_pin: pwm5-pin { + rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm6 { + pwm6_pin: pwm6-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm7 { + pwm7_pin: pwm7-pin { + rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; -- 2.7.4