Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752036AbdHAINo (ORCPT ); Tue, 1 Aug 2017 04:13:44 -0400 Received: from mail-io0-f176.google.com ([209.85.223.176]:38818 "EHLO mail-io0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751757AbdHAINk (ORCPT ); Tue, 1 Aug 2017 04:13:40 -0400 Date: Tue, 1 Aug 2017 17:14:22 +0900 From: AKASHI Takahiro To: Pratyush Anand Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, will.deacon@arm.com, huawei.libin@huawei.com, Alexander Shishkin , Arnaldo Carvalho de Melo , Ingo Molnar , linux-kernel@vger.kernel.org, Peter Zijlstra Subject: Re: [PATCH v3 0/5] ARM64: disable irq between breakpoint and step exception Message-ID: <20170801081420.GB7745@linaro.org> Mail-Followup-To: AKASHI Takahiro , Pratyush Anand , linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, will.deacon@arm.com, huawei.libin@huawei.com, Alexander Shishkin , Arnaldo Carvalho de Melo , Ingo Molnar , linux-kernel@vger.kernel.org, Peter Zijlstra References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2032 Lines: 46 Hi Pratyush, On Mon, Jul 31, 2017 at 04:10:28PM +0530, Pratyush Anand wrote: > v2 -> v3 > - Moved step_needed from uapi structure to kernel only structure > - Re-enable interrupt if stepped instruction faults > - Modified register_wide_hw_breakpoint() to accept step_needed arg > v2 was here: http://marc.info/?l=linux-arm-kernel&m=149942910730496&w=2 > > v1 -> v2: > - patch 1 of v1 has been modified to patch 1-3 of v2. > - Introduced a new event attribute step_needed and implemented > hw_breakpoint_needs_single_step() (patch 1) > - Replaced usage of is_default_overflow_handler() with > hw_breakpoint_needs_single_step(). (patch 2) > - Modified sample test to set set step_needed bit field (patch 3) > v1 was here: http://marc.info/?l=linux-arm-kernel&m=149910958418708&w=2 > > samples/hw_breakpoint/data_breakpoint.c passes with x86_64 but fails with > ARM64. Even though it has been NAKed previously on upstream [1, 2], I have > tried to come up with patches which can resolve it for ARM64 as well. > > I noticed that even perf step exception can go into an infinite loop if CPU > receives an interrupt while executing breakpoint/watchpoint handler. So, > event though we are not concerned about above test, we will have to find a > solution for the perf issue. > > This patchset attempts to resolve both the issue. Please review. > Since, it also takes care of SW breakpoint, so I hope kgdb should also be > fine. However, I have not tested that. > @Takahiro: Will it be possible to test these patches for kgdb. I have not yet understood the details of your patch, but I gave it a try and didn't see any difference around the behavior of kgdb's single stepping. I also gave a try to James' patch, but again nothing different as long as kgdb is concerned. (I'm tackling some issue in single stepping at irq's kernel_exit, in particular, 'eret'.) -Takahiro AKASHI > [1] http://marc.info/?l=linux-arm-kernel&m=149580777524910&w=2 > [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-April/425266.html