Date: Tue, 1 Aug 2017 16:31:45 +0300
From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: Michal =?iso-8859-1?Q?Such=E1nek?= <msuchanek@suse.de>
Cc: James Bottomley <jejb@linux.vnet.ibm.com>,
        Christophe Ricard <christophe.ricard@gmail.com>,
        linux-kernel@vger.kernel.org, tpmdd-devel@lists.sourceforge.net,
        apronin@chromium.org
Subject: Re: [tpmdd-devel] tpm: read burstcount from TPM_STS in one 32-bit
 transaction
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On Tue, Jul 25, 2017 at 08:17:58PM +0200, Michal Such?nek wrote:
> On Tue, 25 Jul 2017 10:36:11 -0700
> James Bottomley <jejb@linux.vnet.ibm.com> wrote:
> 
> > On Tue, 2017-07-25 at 15:04 +0200, Michal Such?nek wrote:
> > > Hello,
> > > 
> > > in commit 9754d45e9970 ("tpm: read burstcount from TPM_STS in one
> > > 32-bit transaction") you change reading of two 8-bit values to one
> > > 32bit read. This is obviously wrong wrt endianess unless the
> > > underlying tpm_tis_read32 does endian conversion.?  
> > 
> > Some of the bus read primitives do do endianness conversions. ?The
> > problem is with the SPI attachment, which has unclear endianness. ?A
> > standard PCI bus attachment uses ioread32() which automatically
> > transforms from a little endian bus to the cpu endianness, however SPI
> > is forced to transfer the bytes one at a time over the serial bus and
> > then transform. ?The assumption seems to be that the TIS TPM is
> > replying in little endian format when SPI connected.
> > 
> 
> Yes, that makes sense.
> 
> Thanks for clarification.
> 
> Michal

Thank you for reporting this and thanks James for explaining this.

I do not have access to PPC hardware with SPI-TPM.

/Jarkko