Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751960AbdHAPRh (ORCPT ); Tue, 1 Aug 2017 11:17:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33956 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751788AbdHAPRf (ORCPT ); Tue, 1 Aug 2017 11:17:35 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3A169C141D45 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=rkrcmar@redhat.com Date: Tue, 1 Aug 2017 17:17:21 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Bandan Das Cc: kvm@vger.kernel.org, pbonzini@redhat.com, david@redhat.com, jmattson@google.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 3/3] KVM: nVMX: Emulate EPTP switching for the L1 hypervisor Message-ID: <20170801151720.GC302@flask> References: <20170728195245.1018-1-bsd@redhat.com> <20170728195245.1018-4-bsd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170728195245.1018-4-bsd@redhat.com> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 01 Aug 2017 15:17:35 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2210 Lines: 66 2017-07-28 15:52-0400, Bandan Das: > When L2 uses vmfunc, L0 utilizes the associated vmexit to > emulate a switching of the ept pointer by reloading the > guest MMU. > > Signed-off-by: Paolo Bonzini > Signed-off-by: Bandan Das > --- > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > @@ -7767,6 +7781,85 @@ static int handle_preemption_timer(struct kvm_vcpu *vcpu) > return 1; > } > > +static bool check_ept_address_valid(struct kvm_vcpu *vcpu, u64 address) > +{ > + struct vcpu_vmx *vmx = to_vmx(vcpu); > + u64 mask = VMX_EPT_RWX_MASK; > + int maxphyaddr = cpuid_maxphyaddr(vcpu); > + struct kvm_mmu *mmu = vcpu->arch.walk_mmu; > + > + /* Check for execute_only validity */ > + if ((address & mask) == VMX_EPT_EXECUTABLE_MASK) { > + if (!(vmx->nested.nested_vmx_ept_caps & > + VMX_EPT_EXECUTE_ONLY_BIT)) > + return false; > + } This checks looks wrong ... bits 0:2 define the memory type: 0 = Uncacheable (UC) 6 = Write-back (WB) If those are supported MSR IA32_VMX_EPT_VPID_CAP, so I think it should return false when (address & 0x7) == 0 && !(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT)) the same for 6 and VMX_EPTP_WB_BIT and unconditionally for the remaining types. Btw. when is TLB flushed after EPTP switching? > @@ -10354,10 +10456,20 @@ static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) > vmx->nested.nested_vmx_entry_ctls_high)) > return VMXERR_ENTRY_INVALID_CONTROL_FIELD; > > - if (nested_cpu_has_vmfunc(vmcs12) && > - (vmcs12->vm_function_control & > - ~vmx->nested.nested_vmx_vmfunc_controls)) > - return VMXERR_ENTRY_INVALID_CONTROL_FIELD; > + if (nested_cpu_has_vmfunc(vmcs12)) { > + if (vmcs12->vm_function_control & > + ~vmx->nested.nested_vmx_vmfunc_controls) > + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; > + > + if (nested_cpu_has_eptp_switching(vmcs12)) { > + if (!nested_cpu_has_ept(vmcs12) || > + (vmcs12->eptp_list_address >> > + cpuid_maxphyaddr(vcpu)) || > + !IS_ALIGNED(vmcs12->eptp_list_address, 4096)) page_address_valid() would make this check a bit nicer, thanks. > + return VMXERR_ENTRY_INVALID_CONTROL_FIELD;