Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752025AbdHARjo (ORCPT ); Tue, 1 Aug 2017 13:39:44 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:57499 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751832AbdHARjm (ORCPT ); Tue, 1 Aug 2017 13:39:42 -0400 Subject: Re: [PATCH 2/2] iommu/omap: Use DMA-API for performing cache flushes To: Josue Albarran , Joerg Roedel CC: , , Laurent Pinchart , , References: <1501274954-20973-1-git-send-email-j-albarran@ti.com> <1501274954-20973-3-git-send-email-j-albarran@ti.com> From: Suman Anna Message-ID: <9e59b00e-a6d9-b0a8-8da6-6724d93c3e58@ti.com> Date: Tue, 1 Aug 2017 12:38:10 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1501274954-20973-3-git-send-email-j-albarran@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [128.247.58.153] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 824 Lines: 20 On 07/28/2017 03:49 PM, Josue Albarran wrote: > The OMAP IOMMU driver was using ARM assembly code directly for > flushing the MMU page table entries from the caches. This caused > MMU faults on OMAP4 (Cortex-A9 based SoCs) as L2 caches were not > handled due to the presence of a PL310 L2 Cache Controller. These > faults were however not seen on OMAP5/DRA7 SoCs (Cortex-A15 based > SoCs). > > The OMAP IOMMU driver is adapted to use the DMA Streaming API > instead now to flush the page table/directory table entries from > the CPU caches. This ensures that the devices always see the > updated page table entries. The outer caches are now addressed > automatically with the usage of the DMA API. > > Signed-off-by: Josue Albarran Thanks for fixing this, Acked-by: Suman Anna [snip]