Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752506AbdHBIcj (ORCPT ); Wed, 2 Aug 2017 04:32:39 -0400 Received: from regular1.263xmail.com ([211.150.99.134]:56172 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752322AbdHBIch (ORCPT ); Wed, 2 Aug 2017 04:32:37 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: andy.yan@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: andy.yan@rock-chips.com X-UNIQUE-TAG: <9b4c94807f2e44168f4a112c3cefa447> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Andy Yan To: heiko@sntech.de Cc: robh+dt@kernel.org, shawn.lin@rock-chips.com, zhangqing@rock-chips.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andy Yan Subject: [PATCH v2 04/23] clk: rockchip: support more rates for cpuclk Date: Wed, 2 Aug 2017 16:32:23 +0800 Message-Id: <1501662743-11920-1-git-send-email-andy.yan@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501662303-11687-1-git-send-email-andy.yan@rock-chips.com> References: <1501662303-11687-1-git-send-email-andy.yan@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1884 Lines: 60 From: Elaine Zhang fix up the cpuclk rates table for support more freqs. fix up the mux_core_mask describe error. Signed-off-by: Elaine Zhang Signed-off-by: Andy Yan --- Changes in v2: - split the new added clks and rename. drivers/clk/rockchip/clk-rv1108.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c index 7c05ab3..3c670db 100644 --- a/drivers/clk/rockchip/clk-rv1108.c +++ b/drivers/clk/rockchip/clk-rv1108.c @@ -93,9 +93,24 @@ static struct rockchip_pll_rate_table rv1108_pll_rates[] = { } static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { - RV1108_CPUCLK_RATE(816000000, 4), - RV1108_CPUCLK_RATE(600000000, 4), - RV1108_CPUCLK_RATE(312000000, 4), + RV1108_CPUCLK_RATE(1608000000, 7), + RV1108_CPUCLK_RATE(1512000000, 7), + RV1108_CPUCLK_RATE(1488000000, 5), + RV1108_CPUCLK_RATE(1416000000, 5), + RV1108_CPUCLK_RATE(1392000000, 5), + RV1108_CPUCLK_RATE(1296000000, 5), + RV1108_CPUCLK_RATE(1200000000, 5), + RV1108_CPUCLK_RATE(1104000000, 5), + RV1108_CPUCLK_RATE(1008000000, 5), + RV1108_CPUCLK_RATE(912000000, 5), + RV1108_CPUCLK_RATE(816000000, 3), + RV1108_CPUCLK_RATE(696000000, 3), + RV1108_CPUCLK_RATE(600000000, 3), + RV1108_CPUCLK_RATE(500000000, 3), + RV1108_CPUCLK_RATE(408000000, 1), + RV1108_CPUCLK_RATE(312000000, 1), + RV1108_CPUCLK_RATE(216000000, 1), + RV1108_CPUCLK_RATE(96000000, 1), }; static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { @@ -105,7 +120,7 @@ static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { .mux_core_alt = 1, .mux_core_main = 0, .mux_core_shift = 8, - .mux_core_mask = 0x1, + .mux_core_mask = 0x3, }; PNAME(mux_pll_p) = { "xin24m", "xin24m"}; -- 2.7.4