Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752114AbdHBX01 (ORCPT ); Wed, 2 Aug 2017 19:26:27 -0400 Received: from LGEAMRELO12.lge.com ([156.147.23.52]:36604 "EHLO lgeamrelo12.lge.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751791AbdHBX00 (ORCPT ); Wed, 2 Aug 2017 19:26:26 -0400 X-Original-SENDERIP: 156.147.1.126 X-Original-MAILFROM: minchan@kernel.org X-Original-SENDERIP: 10.177.220.163 X-Original-MAILFROM: minchan@kernel.org Date: Thu, 3 Aug 2017 08:26:24 +0900 From: Minchan Kim To: Nadav Amit Cc: linux-mm@kvack.org, nadav.amit@gmail.com, linux-kernel@vger.kernel.org, akpm@linux-foundation.org Subject: Re: [PATCH v6 0/7] fixes of TLB batching races Message-ID: <20170802232624.GB32020@bbox> References: <20170802000818.4760-1-namit@vmware.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170802000818.4760-1-namit@vmware.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1311 Lines: 26 On Tue, Aug 01, 2017 at 05:08:11PM -0700, Nadav Amit wrote: > It turns out that Linux TLB batching mechanism suffers from various races. > Races that are caused due to batching during reclamation were recently > handled by Mel and this patch-set deals with others. The more fundamental > issue is that concurrent updates of the page-tables allow for TLB flushes > to be batched on one core, while another core changes the page-tables. > This other core may assume a PTE change does not require a flush based on > the updated PTE value, while it is unaware that TLB flushes are still > pending. > > This behavior affects KSM (which may result in memory corruption) and > MADV_FREE and MADV_DONTNEED (which may result in incorrect behavior). A > proof-of-concept can easily produce the wrong behavior of MADV_DONTNEED. > Memory corruption in KSM is harder to produce in practice, but was observed > by hacking the kernel and adding a delay before flushing and replacing the > KSM page. > > Finally, there is also one memory barrier missing, which may affect > architectures with weak memory model. > > v5 -> v6: > * Combining with Minchan Kim's patch set, adding ack's (Andrew) > * Minor: missing header, typos (Nadav) > * Renaming arch_generic_tlb_finish_mmu (Mel) Thanks for intergrating/correction, Nadav.