Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751704AbdHCIoA (ORCPT ); Thu, 3 Aug 2017 04:44:00 -0400 Received: from 18.mo3.mail-out.ovh.net ([87.98.172.162]:51046 "EHLO 18.mo3.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751087AbdHCIn6 (ORCPT ); Thu, 3 Aug 2017 04:43:58 -0400 X-Greylist: delayed 3606 seconds by postgrey-1.27 at vger.kernel.org; Thu, 03 Aug 2017 04:43:57 EDT Subject: Re: [PATCH 1/1] cpufreq: imx6q: imx6ull: use PLL1 for frequency higher than 528MHz To: Shawn Guo , Anson Huang , Leonard Crestez Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Viresh Kumar , "Rafael J. Wysocki" , Julien Boibessot , Fabio Estevam , linux-arm-kernel@lists.infradead.org References: <1501230993-15812-1-git-send-email-sebastien.szymanski@armadeus.com> <20170803020320.GG31819@dragon> From: =?UTF-8?Q?S=c3=a9bastien_Szymanski?= Message-ID: <737b6166-1594-677b-1a08-4f9b795d9410@armadeus.com> Date: Thu, 3 Aug 2017 09:32:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: <20170803020320.GG31819@dragon> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-Ovh-Tracer-Id: 14975876136014730492 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrjedvgdduvdehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3597 Lines: 107 Hello, On 08/03/2017 04:03 AM, Shawn Guo wrote: > On Fri, Jul 28, 2017 at 10:36:33AM +0200, Sébastien Szymanski wrote: >> Setting the frequency higher than 528Mhz actually sets the ARM >> clock to 528MHz. That's because PLL2 is used as the root clock when the >> frequency is higher than 396MHz. >> >> cpupower frequency-set -f 792000 >> >> arm_clk_root on the CCM_CLKO2 signal is 528MHz instead of 792MHz. >> >> [ 61.606383] cpu cpu0: 396 MHz, 1025 mV --> 792 MHz, 1225 mV >> >> pll2 1 1 528000000 0 0 >> pll2_bypass 1 1 528000000 0 0 >> pll2_bus 3 3 528000000 0 0 >> ca7_secondary_sel 1 1 528000000 0 0 >> step 1 1 528000000 0 0 >> pll1_sw 1 1 528000000 0 0 >> arm 1 1 528000000 0 0 >> >> Fixes this by using the PLL1 as the root clock when the frequency is >> higher than 528MHz. >> >> cpupower frequency-set -f 792000 >> >> arm_clk_root on the CCM_CLKO2 signal is now 792MHz as expected. >> >> [ 69.717987] cpu cpu0: 198 MHz, 950 mV --> 792 MHz, 1225 mV >> >> pll1 1 1 792000000 0 0 >> pll1_bypass 1 1 792000000 0 0 >> pll1_sys 1 1 792000000 0 0 >> pll1_sw 1 1 792000000 0 0 >> arm 1 1 792000000 0 0 >> >> Signed-off-by: Sébastien Szymanski > > Can you please specify on which SoCs you are seeing this problem? And I > would like invite Anson and Leonard to review it. My SoC is MCIMX6Y2CVM08AA which is a 792MHz i.MX6ULL. I forgot to mention that I added the following operating points in my device tree: operating-points: 792000 1225000 fsl,soc-operating-points: 792000 1175000 Best regards, > > Shawn > >> --- >> drivers/cpufreq/imx6q-cpufreq.c | 11 +++++++++-- >> 1 file changed, 9 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c >> index b6edd3c..e5fba50 100644 >> --- a/drivers/cpufreq/imx6q-cpufreq.c >> +++ b/drivers/cpufreq/imx6q-cpufreq.c >> @@ -18,6 +18,7 @@ >> >> #define PU_SOC_VOLTAGE_NORMAL 1250000 >> #define PU_SOC_VOLTAGE_HIGH 1275000 >> +#define FREQ_528_MHZ 528000000 >> #define FREQ_1P2_GHZ 1200000000 >> >> static struct regulator *arm_reg; >> @@ -110,14 +111,20 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) >> * voltage of 528MHz, so lower the CPU frequency to one >> * half before changing CPU frequency. >> */ >> - clk_set_rate(arm_clk, (old_freq >> 1) * 1000); >> - clk_set_parent(pll1_sw_clk, pll1_sys_clk); >> + if ((old_freq * 1000) <= FREQ_528_MHZ) { >> + clk_set_rate(arm_clk, (old_freq >> 1) * 1000); >> + clk_set_parent(pll1_sw_clk, pll1_sys_clk); >> + } >> if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) >> clk_set_parent(secondary_sel_clk, pll2_bus_clk); >> else >> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); >> clk_set_parent(step_clk, secondary_sel_clk); >> clk_set_parent(pll1_sw_clk, step_clk); >> + if (freq_hz > FREQ_528_MHZ) { >> + clk_set_rate(pll1_sys_clk, freq_hz); >> + clk_set_parent(pll1_sw_clk, pll1_sys_clk); >> + } >> } else { >> clk_set_parent(step_clk, pll2_pfd2_396m_clk); >> clk_set_parent(pll1_sw_clk, step_clk); >> -- >> 2.7.3 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Sébastien Szymanski Software engineer, Armadeus Systems Tel: +33 (0)9 72 29 41 44 Fax: +33 (0)9 72 28 79 26