Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751324AbdHDG7I (ORCPT ); Fri, 4 Aug 2017 02:59:08 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:39009 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751269AbdHDG7H (ORCPT ); Fri, 4 Aug 2017 02:59:07 -0400 Subject: Re: update timer frequencies To: Thomas Gleixner CC: Viresh Kumar , "linux-kernel@vger.kernel.org" , "daniel.lezcano@linaro.org" , "john.stultz@linaro.org" , "linux-pm@vger.kernel.org" , "linux-snps-arc@lists.infradead.org" , Peter Zijlstra , Alexey Brodkin Newsgroups: gmane.linux.kernel,gmane.linux.power-management.general,gmane.linux.kernel.arc References: <1489137441.2333.46.camel@synopsys.com> From: Vineet Gupta Message-ID: Date: Fri, 4 Aug 2017 12:28:43 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.12.196.12] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1635 Lines: 40 Hi Thomas, On 03/10/2017 03:58 PM, Thomas Gleixner wrote: > Vlad, > > On Fri, 10 Mar 2017, Vlad Zakharov wrote: >> >> I am trying to implement a cpufreq driver for ARC CPUs. The point is >> that ARC timers (including those are used for timekeeping) are driven by >> the same clock as ARC CPU core(s). > > To be honest: That's broken by design and you really should go and tell > your hardware folks to fix that. Proper timekeeping is essential for any > Operating System (not only Linux). > > It's well known for more than TWO decades that changing the frequency of > the timekeeper clocksource is a complete disaster, but obviously every > hardware vendor has to learn that the hard way instead of simply learning > from history. > ... > > Your hardware design is broken by making the clocksource clock depend on > the CPU frequency. Tell your hardware people to fix that or just use a > seperate independent clocksource. The hardware is being changed and I had a couple of questions to help do it right: 1. The clocksource timers TIMER1, GFRC, RTC etc will now be clocked independent of core using a fixed clk. Is there some magic freq value which best works so we can recommend that to implementors. AFAIKR ARM has 24 MHz. 2. I'm not sure if the timer generating interrupts (periodic or oneshot) needs to be fed invariant fixed clk or dynamic core clk. Naively it should follow the core - but what happens to scheduled timers (say TCP timeouts): if this clk changes - they need to be canceled/updated. If it doesn't then the notion of timing is broken ? I'm likely not thinking this through correctly. Thx, -Vineet