Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751583AbdHGBp6 (ORCPT ); Sun, 6 Aug 2017 21:45:58 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:45069 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751378AbdHGBp4 (ORCPT ); Sun, 6 Aug 2017 21:45:56 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: huibin.hong@rock-chips.com X-FST-TO: sofia-kernel.list@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: huibin.hong@rock-chips.com X-UNIQUE-TAG: <976a1719d79c0b59a10eaa5770ae914a> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Huibin Hong To: sofia-kernel.list@rock-chips.com Cc: huangtao@rock-chips.com, Huibin Hong , Heiko Stuebner , Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] RM: dts: rockchip: rk322x: add spi node and spi pinctrl Date: Mon, 7 Aug 2017 09:45:11 +0800 Message-Id: <1502070311-19663-1-git-send-email-huibin.hong@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2061 Lines: 86 Add spi node and spi pinctrl for rk322x Signed-off-by: Huibin Hong --- arch/arm/boot/dts/rk322x.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index f3e4ffd..1a7afef 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -55,6 +55,7 @@ serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; + spi0 = &spi0; }; cpus { @@ -361,6 +362,19 @@ status = "disabled"; }; + spi0: spi@11090000 { + compatible = "rockchip,rk3228-spi"; + reg = <0x11090000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + status = "disabled"; + }; + wdt: watchdog@110a0000 { compatible = "snps,dw-wdt"; reg = <0x110a0000 0x100>; @@ -797,6 +811,42 @@ }; }; + spi-0 { + spi0_clk: spi0-clk { + rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi-1 { + spi1_clk: spi1-clk { + rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + i2s1 { i2s1_bus: i2s1-bus { rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, -- 1.9.1