Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751945AbdHGBq7 (ORCPT ); Sun, 6 Aug 2017 21:46:59 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:49929 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751761AbdHGBqx (ORCPT ); Sun, 6 Aug 2017 21:46:53 -0400 From: Chris Packham To: robh+dt@kernel.org, gregory.clement@free-electrons.com, bp@alien8.de, jlu@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chris Packham , Mark Rutland , devicetree@vger.kernel.org Subject: [RESEND PATCH 2/4] dt-bindings: add "reduced-width" property for Armada XP SDRAM controller Date: Mon, 7 Aug 2017 13:46:39 +1200 Message-Id: <20170807014641.4003-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> References: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1172 Lines: 27 Some SoC implementations that use this controller have a reduced pin count so the meaning of "full" and "half" with change. Signed-off-by: Chris Packham --- .../bindings/memory-controllers/mvebu-sdram-controller.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt index 89657d1d4cd4..3041868321c8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt @@ -13,6 +13,12 @@ Required properties: - reg: a resource specifier for the register space, which should include all SDRAM controller registers as per the datasheet. +Optional properties: + - marvell,reduced-width: some SoCs that use this SDRAM controller have + a reduced pin count. On such systems "full" width is 32-bits and + "half" width is 16-bits. Set this property to indicate that the SoC + used is such a system. + Example: sdramc@1400 { -- 2.13.0