Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752125AbdHHLM5 (ORCPT ); Tue, 8 Aug 2017 07:12:57 -0400 Received: from mail-dm3nam03on0060.outbound.protection.outlook.com ([104.47.41.60]:58450 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751921AbdHHLMx (ORCPT ); Tue, 8 Aug 2017 07:12:53 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Ravi Shankar Jonnalagadda To: , , , , , , , , , , , , Subject: [PATCH 0/4] ZynqMP PS PCIe DMA Driver Date: Tue, 8 Aug 2017 16:42:15 +0530 Message-ID: <1502190739-13474-1-git-send-email-vjonnal@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.1.0.1062-23244.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(39840400002)(39860400002)(39410400002)(39850400002)(39450400003)(39400400002)(2980300002)(438002)(189002)(199003)(103686004)(6666003)(81166006)(8676002)(8936002)(50226002)(626005)(33646002)(81156014)(6266002)(5660300001)(52956003)(38730400002)(356003)(305945005)(36756003)(2201001)(36386004)(45336002)(46386002)(90966002)(63266004)(2906002)(50986999)(106466001)(189998001)(478600001)(42186005)(50466002)(48376002)(47776003)(5003940100001)(107986001)(921003)(1121003)(5001870100001)(2101003)(83996005);DIR:OUT;SFP:1101;SCL:1;SRVR:BLUPR02MB519;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;PTR:xapps1.xilinx.com,unknown-60-100.xilinx.com;MX:1;A:1;LANG:en; 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These devices can be configured as either PCIe Endpoints or as PCIe Root Complex. This patch series shall provide a driver to initiate transactions using this DMA. Single platform driver shall handle both EndPoint and Root DMA transfers. Patch 1 enables Root DMA register translation and interrupts Patch 2 corrects styling errors seen with checkpatch Patch 3 adds DMA driver functionality for both PCI end points and Root DMA Patch 4 describes device tree bindings for Root DMA Ravi Shankar Jonnalagadda (4): PCI:xilinx-nwl: Enable Root DMA PCI:xilinx-nwl: Correcting Styling checks PCI: ZYNQMP PS PCIe DMA driver: Adding support for DMA driver PCI: ZYNQMP PS PCIe DMA driver: Devicetree binding for Root DMA .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 + drivers/dma/Kconfig | 12 + drivers/dma/xilinx/Makefile | 2 + drivers/dma/xilinx/xilinx_ps_pcie.h | 43 + drivers/dma/xilinx/xilinx_ps_pcie_main.c | 200 ++ drivers/dma/xilinx/xilinx_ps_pcie_platform.c | 3059 ++++++++++++++++++++ drivers/pci/host/pcie-xilinx-nwl.c | 23 +- include/linux/dma/xilinx_ps_pcie_dma.h | 69 + 8 files changed, 3471 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie.h create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_main.c create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_platform.c create mode 100644 include/linux/dma/xilinx_ps_pcie_dma.h -- 2.1.1