Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752523AbdHHUU1 (ORCPT ); Tue, 8 Aug 2017 16:20:27 -0400 Received: from mail.kernel.org ([198.145.29.99]:55274 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752188AbdHHUUZ (ORCPT ); Tue, 8 Aug 2017 16:20:25 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF82322DA7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=helgaas@kernel.org Date: Tue, 8 Aug 2017 15:20:22 -0500 From: Bjorn Helgaas To: honghui.zhang@mediatek.com Cc: bhelgaas@google.com, robh@kerenl.org, robh+dt@kernel.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com, ryder.lee@mediatek.com, youlin.pei@mediatek.com, hongkun.cao@mediatek.com, sean.wang@mediatek.com, xinping.qian@mediatek.com, yt.shen@mediatek.com, yong.wu@mediatek.com Subject: Re: [PATCH v3 5/6] PCI: mediatek: Add new generation controller support Message-ID: <20170808202022.GK16580@bhelgaas-glaptop.roam.corp.google.com> References: <2adcb5f915eb8bd5817592ea32974eb25da02e4f.1501846816.git.honghui.zhang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2adcb5f915eb8bd5817592ea32974eb25da02e4f.1501846816.git.honghui.zhang@mediatek.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 673 Lines: 14 On Fri, Aug 04, 2017 at 08:06:41PM +0800, honghui.zhang@mediatek.com wrote: > From: Ryder Lee > > MediaTek's PCIe host controller has two generation HWs, the new > generation HW has two root ports, it shares most probing flow with the > legacy controller. But the read/write config space logical is different > from the legacy controller. The per-port register must be touched for > read/write config space, And the per-port register base are in separate > address space. Can you also include the new controller IDs ("MT7622/MT2712"?) in the subject line of this patch? > Add support for new Gen2 controller which can be found on MT7622/MT2712.