Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754326AbdHIRB6 (ORCPT ); Wed, 9 Aug 2017 13:01:58 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:39428 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754136AbdHIQyt (ORCPT ); Wed, 9 Aug 2017 12:54:49 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Eugenia Emantayev , Saeed Mahameed Subject: [PATCH 4.12 094/106] net/mlx5e: Add missing support for PTP_CLK_REQ_PPS request Date: Wed, 9 Aug 2017 09:53:18 -0700 Message-Id: <20170809164530.247011316@linuxfoundation.org> X-Mailer: git-send-email 2.14.0 In-Reply-To: <20170809164515.714288642@linuxfoundation.org> References: <20170809164515.714288642@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3255 Lines: 95 4.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Eugenia Emantayev [ Upstream commit cf5033089b078303b102b65e3ccbbfa3ce0f4367 ] Add the missing option to enable the PTP_CLK_PPS function. In this case pin should be configured as 1PPS IN first and then it will be connected to PPS mechanism. Events will be reported as PTP_CLOCK_PPSUSR events to relevant sysfs. Fixes: ee7f12205abc ('net/mlx5e: Implement 1PPS support') Signed-off-by: Eugenia Emantayev Signed-off-by: Saeed Mahameed Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_clock.c | 20 ++++++++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 1 - 3 files changed, 21 insertions(+), 1 deletion(-) --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -266,6 +266,7 @@ struct mlx5e_pps { u8 pin_caps[MAX_PIN_NUM]; struct work_struct out_work; u64 start[MAX_PIN_NUM]; + u8 enabled; }; struct mlx5e_tstamp { --- a/drivers/net/ethernet/mellanox/mlx5/core/en_clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_clock.c @@ -394,6 +394,17 @@ static int mlx5e_perout_configure(struct MLX5E_EVENT_MODE_REPETETIVE & on); } +static int mlx5e_pps_configure(struct ptp_clock_info *ptp, + struct ptp_clock_request *rq, + int on) +{ + struct mlx5e_tstamp *tstamp = + container_of(ptp, struct mlx5e_tstamp, ptp_info); + + tstamp->pps_info.enabled = !!on; + return 0; +} + static int mlx5e_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) @@ -403,6 +414,8 @@ static int mlx5e_ptp_enable(struct ptp_c return mlx5e_extts_configure(ptp, rq, on); case PTP_CLK_REQ_PEROUT: return mlx5e_perout_configure(ptp, rq, on); + case PTP_CLK_REQ_PPS: + return mlx5e_pps_configure(ptp, rq, on); default: return -EOPNOTSUPP; } @@ -448,6 +461,7 @@ static int mlx5e_init_pin_config(struct return -ENOMEM; tstamp->ptp_info.enable = mlx5e_ptp_enable; tstamp->ptp_info.verify = mlx5e_ptp_verify; + tstamp->ptp_info.pps = 1; for (i = 0; i < tstamp->ptp_info.n_pins; i++) { snprintf(tstamp->ptp_info.pin_config[i].name, @@ -499,6 +513,12 @@ void mlx5e_pps_event_handler(struct mlx5 switch (tstamp->ptp_info.pin_config[pin].func) { case PTP_PF_EXTTS: + if (tstamp->pps_info.enabled) { + event->type = PTP_CLOCK_PPSUSR; + event->pps_times.ts_real = ns_to_timespec64(event->timestamp); + } else { + event->type = PTP_CLOCK_EXTTS; + } ptp_clock_event(tstamp->ptp, event); break; case PTP_PF_PEROUT: --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -365,7 +365,6 @@ static void mlx5e_async_event(struct mlx break; case MLX5_DEV_EVENT_PPS: eqe = (struct mlx5_eqe *)param; - ptp_event.type = PTP_CLOCK_EXTTS; ptp_event.index = eqe->data.pps.pin; ptp_event.timestamp = timecounter_cyc2time(&priv->tstamp.clock,